Home
last modified time | relevance | path

Searched refs:IntID (Results 1 – 18 of 18) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonMapAsm2IntrinV62.gen.td9 multiclass T_VR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
10 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
12 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, IntRegs:$src2),
16 multiclass T_VVL_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
17 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),
19 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
24 multiclass T_VV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
25 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
27 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2),
31 multiclass T_WW_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
[all …]
H A DHexagonIntrinsicsV60.td84 multiclass T_R_pat <InstHexagon MI, Intrinsic IntID> {
85 def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>;
86 def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
90 multiclass T_V_pat <InstHexagon MI, Intrinsic IntID> {
91 def: Pat<(IntID HvxVR:$src1),
94 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1),
98 multiclass T_W_pat <InstHexagon MI, Intrinsic IntID> {
99 def: Pat<(IntID HvxWR:$src1),
102 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1),
106 multiclass T_Q_pat <InstHexagon MI, Intrinsic IntID> {
[all …]
H A DHexagonIntrinsics.td11 class T_R_pat <InstHexagon MI, Intrinsic IntID>
12 : Pat <(IntID I32:$Rs),
15 class T_RR_pat <InstHexagon MI, Intrinsic IntID>
16 : Pat <(IntID I32:$Rs, I32:$Rt),
19 class T_RP_pat <InstHexagon MI, Intrinsic IntID>
20 : Pat <(IntID I32:$Rs, I64:$Rt),
143 class S2op_tableidx_pat <Intrinsic IntID, InstHexagon OutputInst,
145 : Pat <(IntID I32:$src1, I32:$src2, u4_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4),
186 class T_stb_pat <InstHexagon MI, Intrinsic IntID, PatLeaf Val>
187 : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru),
[all …]
H A DHexagonOptimizeSZextends.cpp47 bool intrinsicAlreadySextended(Intrinsic::ID IntID);
56 bool HexagonOptimizeSZextends::intrinsicAlreadySextended(Intrinsic::ID IntID) { in intrinsicAlreadySextended() argument
57 switch(IntID) { in intrinsicAlreadySextended()
H A DHexagonVectorCombine.cpp103 Value *createHvxIntrinsic(IRBuilder<> &Builder, Intrinsic::ID IntID,
1216 Intrinsic::ID IntID, Type *RetTy, in createHvxIntrinsic() argument
1265 Function *FI = Intrinsic::getDeclaration(F.getParent(), IntID); in createHvxIntrinsic()
H A DHexagonISelLowering.cpp3564 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked in emitLoadLinked() local
3566 Function *Fn = Intrinsic::getDeclaration(M, IntID); in emitLoadLinked()
3588 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked in emitStoreConditional() local
3590 Function *Fn = Intrinsic::getDeclaration(M, IntID); in emitStoreConditional()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/ObjCARC/
H A DARCRuntimeEntryPoints.h138 Function *getIntrinsicEntryPoint(Function *&Decl, Intrinsic::ID IntID) { in getIntrinsicEntryPoint() argument
142 return Decl = Intrinsic::getDeclaration(TheModule, IntID); in getIntrinsicEntryPoint()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstrAltivec.td268 class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty>
271 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>;
275 class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
279 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>;
283 class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
288 (IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>;
291 class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
294 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>;
298 class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
302 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/
H A DGlobalValue.h83 IntID((Intrinsic::ID)0U), Parent(nullptr) { in GlobalValue()
156 Intrinsic::ID IntID;
H A DFunction.h205 Intrinsic::ID getIntrinsicID() const LLVM_READONLY { return IntID; } in getIntrinsicID()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/IR/
H A DFunction.cpp407 if (IntID) in Function()
408 setAttributes(Intrinsic::getAttributes(getContext(), IntID)); in Function()
710 return isTargetIntrinsic(IntID); in isTargetIntrinsic()
758 IntID = Intrinsic::not_intrinsic; in recalculateIntrinsicID()
762 IntID = lookupIntrinsicID(Name); in recalculateIntrinsicID()
/netbsd-src/external/apache2/llvm/dist/clang/lib/CodeGen/
H A DCGObjC.cpp2114 llvm::Function *&fn, llvm::Intrinsic::ID IntID, in emitARCValueOperation() argument
2120 fn = CGF.CGM.getIntrinsic(IntID); in emitARCValueOperation()
2140 llvm::Intrinsic::ID IntID) { in emitARCLoadOperation() argument
2142 fn = CGF.CGM.getIntrinsic(IntID); in emitARCLoadOperation()
2165 llvm::Intrinsic::ID IntID, in emitARCStoreOperation() argument
2170 fn = CGF.CGM.getIntrinsic(IntID); in emitARCStoreOperation()
2191 llvm::Intrinsic::ID IntID) { in emitARCCopyOperation() argument
2195 fn = CGF.CGM.getIntrinsic(IntID); in emitARCCopyOperation()
H A DCodeGenFunction.h4150 unsigned IntID);
4153 unsigned IntID);
4165 unsigned IntID);
4167 SmallVectorImpl<llvm::Value *> &Ops, unsigned IntID);
4170 unsigned IntID);
H A DCGBuiltin.cpp7075 llvm::Type *ResTy, unsigned IntID, in packTBLDVectorList() argument
7107 TblF = CGF.CGM.getIntrinsic(IntID, ResTy); in packTBLDVectorList()
8462 unsigned IntID; in EmitSVEPredicateCast() local
8470 IntID = Intrinsic::aarch64_sve_convert_from_svbool; in EmitSVEPredicateCast()
8474 IntID = Intrinsic::aarch64_sve_convert_to_svbool; in EmitSVEPredicateCast()
8479 Function *F = CGM.getIntrinsic(IntID, IntrinsicTy); in EmitSVEPredicateCast()
8487 unsigned IntID) { in EmitSVEGatherLoad() argument
8504 F = CGM.getIntrinsic(IntID, {OverloadedTy, Ops[1]->getType()}); in EmitSVEGatherLoad()
8510 F = CGM.getIntrinsic(IntID, OverloadedTy); in EmitSVEGatherLoad()
8539 unsigned IntID) { in EmitSVEScatterStore() argument
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp1637 SDValue IntID = DAG.getTargetConstant(Intrinsic::riscv_vlse, DL, MVT::i64); in splatPartsI64ThroughStack() local
1638 SDValue Ops[] = {Chain, IntID, StackSlot, in splatPartsI64ThroughStack()
1746 SDValue IntID = in lowerVECTOR_SHUFFLE() local
1748 SDValue Ops[] = {Ld->getChain(), IntID, NewAddr, in lowerVECTOR_SHUFFLE()
4119 SDValue IntID = DAG.getTargetConstant(Intrinsic::riscv_vle_mask, DL, XLenVT); in lowerMLOAD() local
4120 SDValue Ops[] = {Load->getChain(), IntID, PassThru, in lowerMLOAD()
4154 SDValue IntID = DAG.getTargetConstant(Intrinsic::riscv_vse_mask, DL, XLenVT); in lowerMSTORE() local
4157 {Store->getChain(), IntID, Val, Store->getBasePtr(), Mask, VL}, in lowerMSTORE()
4404 unsigned IntID = in lowerMGATHER() local
4407 DAG.getTargetConstant(IntID, DL, XLenVT)}; in lowerMGATHER()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1712 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue()); in computeKnownBitsForTargetNode() local
1713 switch (IntID) { in computeKnownBitsForTargetNode()
16765 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue()); in ReplaceNodeResults() local
16766 switch (IntID) { in ReplaceNodeResults()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp18118 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue()); in computeKnownBitsForTargetNode() local
18119 switch (IntID) { in computeKnownBitsForTargetNode()
/netbsd-src/sys/external/bsd/acpica/dist/
H A Dchanges.txt78 AcpiExec: Added a new command, ?interrupt?. The Interrupt command simulates an interrupt with a IntID (GSIV) equal to the first argument of the call/invocation. The acpiexec code simulates the behavior by OSPM: execute the _EVT method of the GED device associated with that IntID. Submitted by: Jose Marinho jose.marinho@arm.com.