| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1168 EVT InVT = InOp.getValueType(); in SplitVecRes_BITCAST() local
1171 switch (getTypeAction(InVT)) { in SplitVecRes_BITCAST()
1435 EVT InVT = Op.getValueType(); in SplitVecRes_StrictFPOp() local
1436 if (InVT.isVector()) { in SplitVecRes_StrictFPOp()
1439 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) in SplitVecRes_StrictFPOp()
1917 EVT InVT = N->getOperand(OpNo).getValueType(); in SplitVecRes_UnaryOp() local
1918 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) in SplitVecRes_UnaryOp()
2335 EVT InVT = Lo.getValueType(); in SplitVecOp_UnaryOp() local
2338 InVT.getVectorElementCount()); in SplitVecOp_UnaryOp()
2795 EVT InVT = InVec->getValueType(0); in SplitVecOp_TruncateHelper() local
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| H A D | LegalizeTypesGeneric.cpp | 44 EVT InVT = InOp.getValueType(); in ExpandRes_BITCAST() local
48 switch (getTypeAction(InVT)) { in ExpandRes_BITCAST()
66 if (TLI.hasBigEndianPartOrdering(InVT, DL) != in ExpandRes_BITCAST()
89 assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BITCAST"); in ExpandRes_BITCAST()
92 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(InVT); in ExpandRes_BITCAST()
102 if (InVT.isVector() && OutVT.isInteger()) { in ExpandRes_BITCAST()
162 Align InAlign = DAG.getReducedAlign(InVT, /*UseABI=*/false); in ExpandRes_BITCAST()
165 SDValue StackPtr = DAG.CreateStackTemporary(InVT.getStoreSize(), Align); in ExpandRes_BITCAST()
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| H A D | LegalizeIntegerTypes.cpp | 337 EVT InVT = InOp.getValueType(); in PromoteIntRes_BITCAST() local
338 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); in PromoteIntRes_BITCAST()
343 switch (getTypeAction(InVT)) { in PromoteIntRes_BITCAST()
405 unsigned ShiftAmt = NInVT.getSizeInBits() - InVT.getSizeInBits(); in PromoteIntRes_BITCAST()
1062 EVT InVT = N->getOperand(OpNo).getValueType(); in PromoteIntRes_SETCC() local
1065 EVT SVT = getSetCCResultType(InVT); in PromoteIntRes_SETCC()
1071 if (getTypeAction(InVT) == TargetLowering::TypePromoteInteger) { in PromoteIntRes_SETCC()
1072 InVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); in PromoteIntRes_SETCC()
1073 SVT = getSetCCResultType(InVT); in PromoteIntRes_SETCC()
1239 EVT InVT = InOp.getValueType(); in PromoteIntRes_TRUNCATE() local
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| H A D | SelectionDAG.cpp | 3255 EVT InVT = Op.getOperand(0).getValueType(); in computeKnownBits() local
3256 APInt InDemandedElts = DemandedElts.zextOrSelf(InVT.getVectorNumElements()); in computeKnownBits()
3267 EVT InVT = Op.getOperand(0).getValueType(); in computeKnownBits() local
3268 APInt InDemandedElts = DemandedElts.zextOrSelf(InVT.getVectorNumElements()); in computeKnownBits()
3283 EVT InVT = Op.getOperand(0).getValueType(); in computeKnownBits() local
3284 APInt InDemandedElts = DemandedElts.zextOrSelf(InVT.getVectorNumElements()); in computeKnownBits()
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| H A D | DAGCombiner.cpp | 19294 EVT InVT = Vec.getValueType(); in reduceBuildVecToShuffle() local
19306 if (InVT.isSimple() && NearestPow2 > 2 && MaxIndex < NearestPow2 && in reduceBuildVecToShuffle()
19310 InVT.getVectorElementType(), SplitSize); in reduceBuildVecToShuffle()
19453 EVT InVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumElems); in convertBuildVecZextToZext() local
19456 if (LegalTypes && !TLI.isTypeLegal(InVT)) in convertBuildVecZextToZext()
19466 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InVT, In, in convertBuildVecZextToZext()
20291 EVT InVT = V.getValueType(); in visitEXTRACT_SUBVECTOR() local
20293 unsigned EltSize = InVT.getScalarSizeInBits(); in visitEXTRACT_SUBVECTOR()
20297 EVT EltVT = InVT.getVectorElementType(); in visitEXTRACT_SUBVECTOR()
20310 Src = DAG.getNode(ISD::TRUNCATE, SDLoc(N), InVT, Src); in visitEXTRACT_SUBVECTOR()
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| H A D | LegalizeDAG.cpp | 2098 EVT InVT = Node->getOperand(Node->isStrictFPOpcode() ? 1 : 0).getValueType(); in ExpandArgFPLibCall() local
2101 switch (InVT.getSimpleVT().SimpleTy) { in ExpandArgFPLibCall()
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | CodeGenDAGPatterns.h | 276 bool MergeInTypeInfo(TypeSetByHwMode &Out, MVT::SimpleValueType InVT) { in MergeInTypeInfo()
277 return MergeInTypeInfo(Out, TypeSetByHwMode(InVT)); in MergeInTypeInfo()
279 bool MergeInTypeInfo(TypeSetByHwMode &Out, ValueTypeByHwMode InVT) { in MergeInTypeInfo()
280 return MergeInTypeInfo(Out, TypeSetByHwMode(InVT)); in MergeInTypeInfo()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 6369 EVT InVT = In.getValueType(); in getEXTEND_VECTOR_INREG() local
6370 assert(VT.isVector() && InVT.isVector() && "Expected vector VTs."); in getEXTEND_VECTOR_INREG()
6377 if (InVT.getSizeInBits() > 128) { in getEXTEND_VECTOR_INREG()
6378 assert(VT.getSizeInBits() == InVT.getSizeInBits() && in getEXTEND_VECTOR_INREG()
6380 unsigned Scale = VT.getScalarSizeInBits() / InVT.getScalarSizeInBits(); in getEXTEND_VECTOR_INREG()
6383 InVT = In.getValueType(); in getEXTEND_VECTOR_INREG()
6386 if (VT.getVectorNumElements() != InVT.getVectorNumElements()) in getEXTEND_VECTOR_INREG()
20741 MVT InVT = In.getSimpleValueType(); in LowerAVXExtend() local
20745 assert(VT.isVector() && InVT.isVector() && "Expected vector type"); in LowerAVXExtend()
20748 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() && in LowerAVXExtend()
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| H A D | X86InstrAVX512.td | 324 X86VectorVTInfo InVT,
329 !con((ins InVT.RC:$src1), NonTiedIns),
330 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
331 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
333 (vselect_mask InVT.KRCWM:$mask, RHS,
334 (bitconvert InVT.RC:$src1)),
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 1099 MVT InVT = V.getSimpleValueType(); in Select() local
1107 if (InVT.isFixedLengthVector()) in Select()
1108 InVT = TLI.getContainerForFixedLengthVector(InVT); in Select()
1114 InVT, SubVecContainerVT, Idx, TRI); in Select()
1125 unsigned InRegClassID = RISCVTargetLowering::getRegClassIDForVecVT(InVT); in Select()
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| H A D | RISCVISelLowering.cpp | 4164 MVT InVT = Op.getOperand(0).getSimpleValueType(); in lowerFixedLengthVectorSetccToRVV() local
4165 MVT ContainerVT = getContainerForFixedLengthVector(InVT); in lowerFixedLengthVectorSetccToRVV()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 3242 EVT InVT = Op.getOperand(0).getValueType(); in LowerVectorFP_TO_INT() local
3252 unsigned NumElts = InVT.getVectorNumElements(); in LowerVectorFP_TO_INT()
3255 if (InVT.getVectorElementType() == MVT::f16 && in LowerVectorFP_TO_INT()
3265 uint64_t InVTSize = InVT.getFixedSizeInBits(); in LowerVectorFP_TO_INT()
3269 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(), in LowerVectorFP_TO_INT()
3358 EVT InVT = In.getValueType(); in LowerVectorINT_TO_FP() local
3363 if (InVT.getVectorElementType() == MVT::i1) { in LowerVectorINT_TO_FP()
3366 EVT CastVT = getPromotedVTForPredicate(InVT); in LowerVectorINT_TO_FP()
3377 uint64_t InVTSize = InVT.getFixedSizeInBits(); in LowerVectorINT_TO_FP()
3380 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()), in LowerVectorINT_TO_FP()
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| H A D | AArch64ISelDAGToDAG.cpp | 3445 EVT InVT = Node->getOperand(0).getValueType(); in Select() local
3446 if (VT.isScalableVector() || InVT.isFixedLengthVector()) in Select()
3469 EVT InVT = Node->getOperand(1).getValueType(); in Select() local
3470 if (VT.isFixedLengthVector() || InVT.isScalableVector()) in Select()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 3326 EVT InVT = In.getValueType(); in lowerBITCAST() local
3341 if (InVT == MVT::i32 && ResVT == MVT::f32) { in lowerBITCAST()
3357 if (InVT == MVT::f32 && ResVT == MVT::i32) { in lowerBITCAST()
4479 MVT InVT = MVT::getVectorVT(MVT::getIntegerVT(InBytes * 8), in getPermuteNode() local
4481 Op0 = DAG.getNode(ISD::BITCAST, DL, InVT, Op0); in getPermuteNode()
4482 Op1 = DAG.getNode(ISD::BITCAST, DL, InVT, Op1); in getPermuteNode()
4486 Op = DAG.getNode(SystemZISD::PERMUTE_DWORDS, DL, InVT, Op0, Op1, Op2); in getPermuteNode()
4492 Op = DAG.getNode(P.Opcode, DL, InVT, Op0, Op1); in getPermuteNode()
4864 EVT InVT = MVT::getVectorVT(MVT::getIntegerVT(InBits), in insertUnpackIfPrepared() local
4866 SDValue PackedOp = DAG.getNode(ISD::BITCAST, DL, InVT, Op); in insertUnpackIfPrepared()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 2929 EVT InVT = InputOp.getValueType(); in computeLogicOpInGPR() local
2930 return SDValue(CurDAG->getMachineNode(InVT == MVT::i32 ? PPC::RLDICL_32 : in computeLogicOpInGPR()
2931 PPC::RLDICL, dl, InVT, InputOp, in computeLogicOpInGPR()
3074 EVT InVT = LHS.getValueType(); in getCompoundZeroComparisonInGPR() local
3075 bool Is32Bit = InVT == MVT::i32; in getCompoundZeroComparisonInGPR()
3083 dl, InVT, LHS, LHS), 0); in getCompoundZeroComparisonInGPR()
5360 EVT InVT = N->getOperand(0).getValueType(); in Select() local
5361 assert((InVT == MVT::i64 || InVT == MVT::i32) && in Select()
5364 unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDI8_rec : PPC::ANDI_rec; in Select()
5365 SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue, in Select()
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| H A D | PPCISelLowering.cpp | 8402 EVT InVT = Src.getValueType(); in LowerINT_TO_FP() local
8405 isOperationCustom(Op.getOpcode(), InVT)) in LowerINT_TO_FP()
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