| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 62 if (getOpcode() < ISD::BUILTIN_OP_END) in getOperationName()
80 case ISD::DELETED_NODE: return "<<Deleted Node!>>"; in getOperationName()
82 case ISD::PREFETCH: return "Prefetch"; in getOperationName()
83 case ISD::ATOMIC_FENCE: return "AtomicFence"; in getOperationName()
84 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; in getOperationName()
85 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: return "AtomicCmpSwapWithSuccess"; in getOperationName()
86 case ISD::ATOMIC_SWAP: return "AtomicSwap"; in getOperationName()
87 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; in getOperationName()
88 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub"; in getOperationName()
89 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd"; in getOperationName()
[all …]
|
| H A D | LegalizeVectorOps.cpp | 257 if (Op.getOpcode() == ISD::LOAD) { in LegalizeOp()
259 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeOp()
260 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) { in LegalizeOp()
288 } else if (Op.getOpcode() == ISD::STORE) { in LegalizeOp()
332 case ISD::MERGE_VALUES: in LegalizeOp()
340 case ISD::STRICT_##DAGN: in LegalizeOp()
343 if (Op.getOpcode() == ISD::STRICT_SINT_TO_FP || in LegalizeOp()
344 Op.getOpcode() == ISD::STRICT_UINT_TO_FP) in LegalizeOp()
363 case ISD::ADD: in LegalizeOp()
364 case ISD::SUB: in LegalizeOp()
[all …]
|
| H A D | LegalizeDAG.cpp | 316 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) && in ExpandConstantFP()
331 ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx, in ExpandConstantFP()
405 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, in ExpandINSERT_VECTOR_ELT()
423 if (!ISD::isNormalStore(ST)) in OptimizeFloatStore()
441 if (Value.getOpcode() == ISD::TargetConstantFP) in OptimizeFloatStore()
480 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); in OptimizeFloatStore()
505 switch (TLI.getOperationAction(ISD::STORE, VT)) { in LegalizeStoreOps()
529 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT); in LegalizeStoreOps()
532 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value); in LegalizeStoreOps()
586 ISD::SRL, dl, Value.getValueType(), Value, in LegalizeStoreOps()
[all …]
|
| H A D | LegalizeIntegerTypes.cpp | 55 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break; in PromoteIntegerResult()
56 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; in PromoteIntegerResult()
57 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; in PromoteIntegerResult()
58 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break; in PromoteIntegerResult()
59 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break; in PromoteIntegerResult()
60 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break; in PromoteIntegerResult()
61 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; in PromoteIntegerResult()
62 case ISD::Constant: Res = PromoteIntRes_Constant(N); break; in PromoteIntegerResult()
63 case ISD::CTLZ_ZERO_UNDEF: in PromoteIntegerResult()
64 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break; in PromoteIntegerResult()
[all …]
|
| H A D | LegalizeFloatTypes.cpp | 61 case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break; in SoftenFloatResult()
62 case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break; in SoftenFloatResult()
63 case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break; in SoftenFloatResult()
64 case ISD::ConstantFP: R = SoftenFloatRes_ConstantFP(N); break; in SoftenFloatResult()
65 case ISD::EXTRACT_VECTOR_ELT: in SoftenFloatResult()
67 case ISD::FABS: R = SoftenFloatRes_FABS(N); break; in SoftenFloatResult()
68 case ISD::STRICT_FMINNUM: in SoftenFloatResult()
69 case ISD::FMINNUM: R = SoftenFloatRes_FMINNUM(N); break; in SoftenFloatResult()
70 case ISD::STRICT_FMAXNUM: in SoftenFloatResult()
71 case ISD::FMAXNUM: R = SoftenFloatRes_FMAXNUM(N); break; in SoftenFloatResult()
[all …]
|
| H A D | TargetLowering.cpp | 96 if (Value->getOpcode() != ISD::CopyFromReg) in parametersInCSRMatch()
244 if (isOperationLegalOrCustom(ISD::STORE, NewVT) && in findOptimalMemOpLowering()
248 isOperationLegalOrCustom(ISD::STORE, MVT::f64) && in findOptimalMemOpLowering()
294 ISD::CondCode &CCCode, in softenSetCCOperands()
304 ISD::CondCode &CCCode, in softenSetCCOperands()
320 case ISD::SETEQ: in softenSetCCOperands()
321 case ISD::SETOEQ: in softenSetCCOperands()
326 case ISD::SETNE: in softenSetCCOperands()
327 case ISD::SETUNE: in softenSetCCOperands()
332 case ISD::SETGE: in softenSetCCOperands()
[all …]
|
| H A D | DAGCombiner.cpp | 264 assert(N->getOpcode() != ISD::DELETED_NODE && in AddToWorklist()
269 if (N->getOpcode() == ISD::HANDLENODE) in AddToWorklist()
541 SDValue N2, SDValue N3, ISD::CondCode CC,
545 ISD::CondCode CC);
548 SDValue N2, SDValue N3, ISD::CondCode CC);
554 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
651 case ISD::Constant: in getStoreSource()
652 case ISD::ConstantFP: in getStoreSource()
654 case ISD::EXTRACT_VECTOR_ELT: in getStoreSource()
655 case ISD::EXTRACT_SUBVECTOR: in getStoreSource()
[all …]
|
| H A D | LegalizeVectorTypes.cpp | 51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break; in ScalarizeVectorResult()
52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; in ScalarizeVectorResult()
53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break; in ScalarizeVectorResult()
54 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; in ScalarizeVectorResult()
55 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; in ScalarizeVectorResult()
56 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break; in ScalarizeVectorResult()
57 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; in ScalarizeVectorResult()
58 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break; in ScalarizeVectorResult()
59 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break; in ScalarizeVectorResult()
60 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break; in ScalarizeVectorResult()
[all …]
|
| H A D | SelectionDAG.cpp | 141 bool ISD::isConstantSplatVector(const SDNode *N, APInt &SplatVal) { in isConstantSplatVector()
142 if (N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstantSplatVector()
171 bool ISD::isConstantSplatVectorAllOnes(const SDNode *N, bool BuildVectorOnly) { in isConstantSplatVectorAllOnes()
173 while (N->getOpcode() == ISD::BITCAST) in isConstantSplatVectorAllOnes()
176 if (!BuildVectorOnly && N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstantSplatVectorAllOnes()
181 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; in isConstantSplatVectorAllOnes()
220 bool ISD::isConstantSplatVectorAllZeros(const SDNode *N, bool BuildVectorOnly) { in isConstantSplatVectorAllZeros()
222 while (N->getOpcode() == ISD::BITCAST) in isConstantSplatVectorAllZeros()
225 if (!BuildVectorOnly && N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstantSplatVectorAllZeros()
230 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; in isConstantSplatVectorAllZeros()
[all …]
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 206 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getArithmeticInstrCost() local
207 assert(ISD && "Invalid opcode"); in getArithmeticInstrCost()
210 { ISD::FDIV, MVT::f32, 18 }, // divss in getArithmeticInstrCost()
211 { ISD::FDIV, MVT::v4f32, 35 }, // divps in getArithmeticInstrCost()
212 { ISD::FDIV, MVT::f64, 33 }, // divsd in getArithmeticInstrCost()
213 { ISD::FDIV, MVT::v2f64, 65 }, // divpd in getArithmeticInstrCost()
217 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, in getArithmeticInstrCost()
222 { ISD::MUL, MVT::v4i32, 11 }, // pmulld in getArithmeticInstrCost()
223 { ISD::MUL, MVT::v8i16, 2 }, // pmullw in getArithmeticInstrCost()
224 { ISD::FMUL, MVT::f64, 2 }, // mulsd in getArithmeticInstrCost()
[all …]
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 66 setOperationAction(ISD::LOAD, MVT::f32, Promote); in AMDGPUTargetLowering()
67 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32); in AMDGPUTargetLowering()
69 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); in AMDGPUTargetLowering()
70 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
72 setOperationAction(ISD::LOAD, MVT::v3f32, Promote); in AMDGPUTargetLowering()
73 AddPromotedToType(ISD::LOAD, MVT::v3f32, MVT::v3i32); in AMDGPUTargetLowering()
75 setOperationAction(ISD::LOAD, MVT::v4f32, Promote); in AMDGPUTargetLowering()
76 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32); in AMDGPUTargetLowering()
78 setOperationAction(ISD::LOAD, MVT::v5f32, Promote); in AMDGPUTargetLowering()
79 AddPromotedToType(ISD::LOAD, MVT::v5f32, MVT::v5i32); in AMDGPUTargetLowering()
[all …]
|
| H A D | R600ISelLowering.cpp | 44 setOperationAction(ISD::LOAD, MVT::i32, Custom); in R600TargetLowering()
45 setOperationAction(ISD::LOAD, MVT::v2i32, Custom); in R600TargetLowering()
46 setOperationAction(ISD::LOAD, MVT::v4i32, Custom); in R600TargetLowering()
51 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
52 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
53 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
55 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
56 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
57 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
59 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
[all …]
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 401 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getCastInstrCost() local
402 assert(ISD && "Invalid opcode"); in getCastInstrCost()
441 {ISD::SIGN_EXTEND, MVT::i32, MVT::i16, 0}, in getCastInstrCost()
442 {ISD::ZERO_EXTEND, MVT::i32, MVT::i16, 0}, in getCastInstrCost()
443 {ISD::SIGN_EXTEND, MVT::i32, MVT::i8, 0}, in getCastInstrCost()
444 {ISD::ZERO_EXTEND, MVT::i32, MVT::i8, 0}, in getCastInstrCost()
445 {ISD::SIGN_EXTEND, MVT::i16, MVT::i8, 0}, in getCastInstrCost()
446 {ISD::ZERO_EXTEND, MVT::i16, MVT::i8, 0}, in getCastInstrCost()
447 {ISD::SIGN_EXTEND, MVT::i64, MVT::i32, 1}, in getCastInstrCost()
448 {ISD::ZERO_EXTEND, MVT::i64, MVT::i32, 1}, in getCastInstrCost()
[all …]
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| H A D | VEISelDAGToDAG.cpp | 27 inline static VECC::CondCode intCondCode2Icc(ISD::CondCode CC) { in intCondCode2Icc()
31 case ISD::SETEQ: in intCondCode2Icc()
33 case ISD::SETNE: in intCondCode2Icc()
35 case ISD::SETLT: in intCondCode2Icc()
37 case ISD::SETGT: in intCondCode2Icc()
39 case ISD::SETLE: in intCondCode2Icc()
41 case ISD::SETGE: in intCondCode2Icc()
43 case ISD::SETULT: in intCondCode2Icc()
45 case ISD::SETULE: in intCondCode2Icc()
47 case ISD::SETUGT: in intCondCode2Icc()
[all …]
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 61 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); in MSP430TargetLowering()
62 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); in MSP430TargetLowering()
65 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
66 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
67 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
68 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); in MSP430TargetLowering()
69 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); in MSP430TargetLowering()
75 setOperationAction(ISD::SRA, MVT::i8, Custom); in MSP430TargetLowering()
76 setOperationAction(ISD::SHL, MVT::i8, Custom); in MSP430TargetLowering()
77 setOperationAction(ISD::SRL, MVT::i8, Custom); in MSP430TargetLowering()
[all …]
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetTransformInfo.cpp | 582 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getCastInstrCost() local
583 assert(ISD && "Invalid opcode"); in getCastInstrCost()
621 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, in getCastInstrCost()
622 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, in getCastInstrCost()
623 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost()
624 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, in getCastInstrCost()
627 { ISD::TRUNCATE, MVT::nxv2i1, MVT::nxv2i16, 1 }, in getCastInstrCost()
628 { ISD::TRUNCATE, MVT::nxv2i1, MVT::nxv2i32, 1 }, in getCastInstrCost()
629 { ISD::TRUNCATE, MVT::nxv2i1, MVT::nxv2i64, 1 }, in getCastInstrCost()
630 { ISD::TRUNCATE, MVT::nxv4i1, MVT::nxv4i16, 1 }, in getCastInstrCost()
[all …]
|
| H A D | AArch64ISelLowering.cpp | 318 setOperationAction(ISD::SADDSAT, VT, Legal); in AArch64TargetLowering()
319 setOperationAction(ISD::UADDSAT, VT, Legal); in AArch64TargetLowering()
320 setOperationAction(ISD::SSUBSAT, VT, Legal); in AArch64TargetLowering()
321 setOperationAction(ISD::USUBSAT, VT, Legal); in AArch64TargetLowering()
322 setOperationAction(ISD::UREM, VT, Expand); in AArch64TargetLowering()
323 setOperationAction(ISD::SREM, VT, Expand); in AArch64TargetLowering()
324 setOperationAction(ISD::SDIVREM, VT, Expand); in AArch64TargetLowering()
325 setOperationAction(ISD::UDIVREM, VT, Expand); in AArch64TargetLowering()
331 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Legal); in AArch64TargetLowering()
336 setCondCodeAction(ISD::SETO, VT, Expand); in AArch64TargetLowering()
[all …]
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 518 case ISD::ATOMIC_CMP_SWAP: { in getOUTLINE_ATOMIC()
522 case ISD::ATOMIC_SWAP: { in getOUTLINE_ATOMIC()
526 case ISD::ATOMIC_LOAD_ADD: { in getOUTLINE_ATOMIC()
530 case ISD::ATOMIC_LOAD_OR: { in getOUTLINE_ATOMIC()
534 case ISD::ATOMIC_LOAD_CLR: { in getOUTLINE_ATOMIC()
538 case ISD::ATOMIC_LOAD_XOR: { in getOUTLINE_ATOMIC()
568 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET) in getSYNC()
569 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP) in getSYNC()
570 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD) in getSYNC()
571 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB) in getSYNC()
[all …]
|
| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAGNodes.h | 84 namespace ISD {
625 bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
633 return NodeType >= ISD::FIRST_TARGET_STRICTFP_OPCODE;
640 return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE;
644 bool isUndef() const { return NodeType == ISD::UNDEF; }
652 return (NodeType == ISD::INTRINSIC_W_CHAIN ||
653 NodeType == ISD::INTRINSIC_VOID) &&
662 case ISD::STRICT_FP16_TO_FP:
663 case ISD::STRICT_FP_TO_FP16:
665 case ISD::STRICT_##DAGN:
[all …]
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 166 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) in RISCVTargetLowering()
170 setOperationAction(ISD::DYNAMIC_STACKALLOC, XLenVT, Expand); in RISCVTargetLowering()
172 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in RISCVTargetLowering()
173 setOperationAction(ISD::BR_CC, XLenVT, Expand); in RISCVTargetLowering()
174 setOperationAction(ISD::BRCOND, MVT::Other, Custom); in RISCVTargetLowering()
175 setOperationAction(ISD::SELECT_CC, XLenVT, Expand); in RISCVTargetLowering()
177 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); in RISCVTargetLowering()
178 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); in RISCVTargetLowering()
180 setOperationAction(ISD::VASTART, MVT::Other, Custom); in RISCVTargetLowering()
181 setOperationAction(ISD::VAARG, MVT::Other, Expand); in RISCVTargetLowering()
[all …]
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 63 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in M68kTargetLowering()
64 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in M68kTargetLowering()
65 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in M68kTargetLowering()
76 setOperationAction(ISD::MUL, MVT::i8, Promote); in M68kTargetLowering()
77 setOperationAction(ISD::MUL, MVT::i16, Legal); in M68kTargetLowering()
79 setOperationAction(ISD::MUL, MVT::i32, Legal); in M68kTargetLowering()
81 setOperationAction(ISD::MUL, MVT::i32, LibCall); in M68kTargetLowering()
82 setOperationAction(ISD::MUL, MVT::i64, LibCall); in M68kTargetLowering()
85 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM, ISD::UDIVREM, ISD::SDIVREM, in M68kTargetLowering()
86 ISD::MULHS, ISD::MULHU, ISD::UMUL_LOHI, ISD::SMUL_LOHI}) { in M68kTargetLowering()
[all …]
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 51 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); in AVRTargetLowering()
52 setOperationAction(ISD::BlockAddress, MVT::i16, Custom); in AVRTargetLowering()
54 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); in AVRTargetLowering()
55 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); in AVRTargetLowering()
56 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand); in AVRTargetLowering()
57 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand); in AVRTargetLowering()
60 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) { in AVRTargetLowering()
69 setOperationAction(ISD::ADDC, VT, Legal); in AVRTargetLowering()
70 setOperationAction(ISD::SUBC, VT, Legal); in AVRTargetLowering()
71 setOperationAction(ISD::ADDE, VT, Legal); in AVRTargetLowering()
[all …]
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 75 setOperationAction(ISD::LOAD, T, Custom); in WebAssemblyTargetLowering()
76 setOperationAction(ISD::STORE, T, Custom); in WebAssemblyTargetLowering()
81 setOperationAction(ISD::LOAD, T, Custom); in WebAssemblyTargetLowering()
82 setOperationAction(ISD::STORE, T, Custom); in WebAssemblyTargetLowering()
86 setOperationAction(ISD::GlobalAddress, MVTPtr, Custom); in WebAssemblyTargetLowering()
87 setOperationAction(ISD::GlobalTLSAddress, MVTPtr, Custom); in WebAssemblyTargetLowering()
88 setOperationAction(ISD::ExternalSymbol, MVTPtr, Custom); in WebAssemblyTargetLowering()
89 setOperationAction(ISD::JumpTable, MVTPtr, Custom); in WebAssemblyTargetLowering()
90 setOperationAction(ISD::BlockAddress, MVTPtr, Custom); in WebAssemblyTargetLowering()
91 setOperationAction(ISD::BRIND, MVT::Other, Custom); in WebAssemblyTargetLowering()
[all …]
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 43 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_SRet()
56 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_Split_64()
82 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_Ret_Split_64()
106 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_Sparc64_Full()
151 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_Sparc64_Half()
197 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
208 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn_32()
242 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
245 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
293 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn_64()
[all …]
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 163 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); in PPCTargetLowering()
164 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); in PPCTargetLowering()
167 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); in PPCTargetLowering()
170 setOperationAction(ISD::INLINEASM, MVT::Other, Custom); in PPCTargetLowering()
171 setOperationAction(ISD::INLINEASM_BR, MVT::Other, Custom); in PPCTargetLowering()
175 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in PPCTargetLowering()
176 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); in PPCTargetLowering()
180 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal); in PPCTargetLowering()
181 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Legal); in PPCTargetLowering()
186 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); in PPCTargetLowering()
[all …]
|