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Searched refs:INT_MASK (Results 1 – 10 of 10) sorted by relevance

/netbsd-src/sys/arch/bebox/stand/boot/
H A Dfd.c647 u_int INT_MASK; variable
661 outb(INT_CTL1, (INT_MASK = ~(1 << CASCADE_IRQ))); in irq_init()
707 outb(INT_CTL1, INT_MASK); in irq_polling()
/netbsd-src/sys/arch/mips/adm5120/dev/
H A Dif_admsw.c289 REG_WRITE(ADMSW_INT_MASK, INT_MASK); in admsw_reset()
290 REG_WRITE(ADMSW_INT_ST, INT_MASK); in admsw_reset()
1042 REG_WRITE(ADMSW_INT_ST, INT_MASK); in admsw_init()
1087 REG_WRITE(ADMSW_INT_ST, INT_MASK); in admsw_stop()
1090 REG_WRITE(ADMSW_INT_MASK, INT_MASK); in admsw_stop()
H A Dif_admswreg.h225 #define INT_MASK 0x1FDEFFF macro
/netbsd-src/external/gpl3/gdb/dist/sim/ppc/
H A Dpowerpc.igen135 #define PPC_INSN_FROM_SPR(INT_MASK, SPR) \
138 ppc_insn_from_spr(MY_INDEX, cpu_model(processor), INT_MASK, SPR); \
141 #define PPC_INSN_TO_SPR(INT_MASK, SPR) \
144 ppc_insn_to_spr(MY_INDEX, cpu_model(processor), INT_MASK, SPR); \
147 #define PPC_INSN_MFCR(INT_MASK) \
150 ppc_insn_mfcr(MY_INDEX, cpu_model(processor), INT_MASK); \
153 #define PPC_INSN_MTCR(INT_MASK, FXM) \
156 ppc_insn_mtcr(MY_INDEX, cpu_model(processor), INT_MASK, FXM); \
/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dsid.h821 #define INT_MASK 0x6b40 macro
H A Devergreend.h1286 #define INT_MASK 0x6b40 macro
H A Dradeon_evergreen.c4482 WREG32(INT_MASK + crtc_offsets[i], 0); in evergreen_disable_interrupt_state()
4582 rdev, INT_MASK + crtc_offsets[i], in evergreen_irq_set()
H A Dradeon_si.c5972 WREG32(INT_MASK + crtc_offsets[i], 0); in si_disable_interrupt_state()
6126 rdev, INT_MASK + crtc_offsets[i], VBLANK_INT_MASK, in si_irq_set()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Dsid.h825 #define INT_MASK 0x1AD0 macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/
H A Dnavi10_enum.h2077 typedef enum INT_MASK { enum
2080 } INT_MASK; typedef