| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 816 Register HiReg = HiOperand.getReg(); in emitCombineRI() local
824 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
832 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
856 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
867 Register HiReg = HiOperand.getReg(); in emitCombineRR() local
884 .addReg(HiReg, HiRegKillFlag) in emitCombineRR()
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| H A D | HexagonPatterns.td | 124 def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_hi)>;
538 (Combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>;
541 (Combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>;
557 (A2_combine_ll (HiReg $Rs), (LoReg $Rs))>;
875 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
885 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
1070 (A2_swiz (HiReg $Rss)))>;
1108 (HiReg (S2_asl_i_p (Combinew $Rs, $Rt), $S))>;
1110 (HiReg (S2_asl_r_p (Combinew $Rs, $Rt), $Ru))>;
1378 (Combinew (S2_clrbit_i (HiReg $Rs), 31),
[all …]
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| H A D | HexagonIntrinsics.td | 95 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
97 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
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| H A D | HexagonFrameLowering.cpp | 1126 Register HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi); in insertCFIInstructionsAt() local
1128 unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true); in insertCFIInstructionsAt()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.cpp | 272 Register &HiReg) const { in splitReg()
276 HiReg = getSubReg(Reg, AVR::sub_hi); in splitReg()
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| H A D | AVRRegisterInfo.h | 52 void splitReg(Register Reg, Register &LoReg, Register &HiReg) const;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 1874 Register HiReg = MRI->createVirtualRegister(DstRC); in selectG_TRUNC() local
1877 BuildMI(*MBB, I, DL, TII.get(AMDGPU::COPY), HiReg) in selectG_TRUNC()
1886 .addReg(HiReg) // $src0 in selectG_TRUNC()
1900 .addReg(HiReg); in selectG_TRUNC()
1903 .addReg(HiReg) in selectG_TRUNC()
2148 Register HiReg = MRI->createVirtualRegister(RC); in selectG_CONSTANT() local
2153 BuildMI(*BB, &I, DL, TII.get(Opcode), HiReg) in selectG_CONSTANT()
2159 .addReg(HiReg) in selectG_CONSTANT()
2203 Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FNEG() local
2209 BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), HiReg) in selectG_FNEG()
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| H A D | SILoadStoreOptimizer.cpp | 167 Register HiReg; member
1685 assert((TRI->getRegSizeInBits(Addr.Base.HiReg, *MRI) == 32 || in computeBase()
1712 .addReg(Addr.Base.HiReg, 0, Addr.Base.HiSubReg) in computeBase()
1815 Addr.Base.HiReg = BaseHi.getReg(); in processBaseWithConstOffset()
1861 LLVM_DEBUG(dbgs() << " BASE: {" << MAddr.Base.HiReg << ", " in promoteConstantOffsetToImm()
1919 MAddrNext.Base.HiReg != MAddr.Base.HiReg || in promoteConstantOffsetToImm()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 309 Register HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
325 std::swap(LoReg, HiReg); in expandBuildPairF64()
328 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, in expandBuildPairF64()
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| H A D | MipsSEInstrInfo.cpp | 828 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
876 .addReg(HiReg); in expandBuildPairF64()
881 .addReg(HiReg); in expandBuildPairF64()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 5042 unsigned LoReg, HiReg; in Select() local
5056 HiReg = X86::EDX; in Select()
5066 HiReg = X86::RDX; in Select()
5142 assert(HiReg && "Register for high half is not defined!"); in Select()
5143 ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, in Select()
5181 unsigned LoReg, HiReg, ClrReg; in Select() local
5186 LoReg = X86::AL; ClrReg = HiReg = X86::AH; in Select()
5190 LoReg = X86::AX; HiReg = X86::DX; in Select()
5195 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX; in Select()
5199 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX; in Select()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1833 for (int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; --LoReg) { in CMSEPushCalleeSaves() local
1837 .addReg(HiReg, LiveRegs.contains(HiReg) ? 0 : RegState::Undef) in CMSEPushCalleeSaves()
1839 --HiReg; in CMSEPushCalleeSaves()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 6230 Register HiReg = MI.getOperand(1).getReg(); in emitReadCycleWidePseudo() local
6234 BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), HiReg) in emitReadCycleWidePseudo()
6245 .addReg(HiReg) in emitReadCycleWidePseudo()
6266 Register HiReg = MI.getOperand(1).getReg(); in emitSplitF64Pseudo() local
6282 BuildMI(*BB, MI, DL, TII.get(RISCV::LW), HiReg) in emitSplitF64Pseudo()
6301 Register HiReg = MI.getOperand(2).getReg(); in emitBuildPairF64Pseudo() local
6316 .addReg(HiReg, getKillRegState(MI.getOperand(2).isKill())) in emitBuildPairF64Pseudo()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 7458 unsigned Reg, unsigned HiReg, in checkLowRegisterList() argument
7466 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) in checkLowRegisterList()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 11971 Register HiReg = MI.getOperand(1).getReg(); in EmitInstrWithCustomInserter() local
11973 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269); in EmitInstrWithCustomInserter()
11980 .addReg(HiReg) in EmitInstrWithCustomInserter()
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