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Searched refs:HasBaseReg (Results 1 – 22 of 22) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86AsmPrinter.cpp293 bool HasBaseReg = BaseReg.getReg() != 0; in PrintLeaMemReference() local
294 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") && in PrintLeaMemReference()
296 HasBaseReg = false; in PrintLeaMemReference()
299 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in PrintLeaMemReference()
324 if (HasBaseReg) in PrintLeaMemReference()
360 bool HasBaseReg = BaseReg.getReg() != 0; in PrintIntelMemReference() local
361 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") && in PrintIntelMemReference()
363 HasBaseReg = false; in PrintIntelMemReference()
374 if (HasBaseReg) { in PrintIntelMemReference()
392 if (DispVal || (!IndexReg.getReg() && !HasBaseReg)) { in PrintIntelMemReference()
H A DX86ISelLowering.cpp31690 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) in isLegalAddressingMode()
31712 if (AM.HasBaseReg) in isLegalAddressingMode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
H A DLoopStrengthReduce.cpp347 bool HasBaseReg = false; member
467 HasBaseReg = true; in initialMatch()
473 HasBaseReg = true; in initialMatch()
614 if (HasBaseReg && BaseRegs.empty()) { in print()
617 } else if (!HasBaseReg && !BaseRegs.empty()) { in print()
1216 bool HasBaseReg, int64_t Scale,
1379 Offset, F.HasBaseReg, F.Scale, Fixup.UserInst)) in RateFormula()
1633 bool HasBaseReg, int64_t Scale, in isAMCompletelyFolded() argument
1638 HasBaseReg, Scale, AccessTy.AddrSpace, Fixup); in isAMCompletelyFolded()
1647 if (Scale != 0 && HasBaseReg && BaseOffset != 0) in isAMCompletelyFolded()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/
H A DTargetTransformInfoImpl.h200 bool HasBaseReg, int64_t Scale, unsigned AddrSpace,
274 int64_t BaseOffset, bool HasBaseReg, in getScalingFactorCost() argument
278 if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale, in getScalingFactorCost()
865 bool HasBaseReg = (BaseGV == nullptr); variable
914 BaseOffset.sextOrTrunc(64).getSExtValue(), HasBaseReg, Scale,
H A DTargetTransformInfo.h606 bool HasBaseReg, int64_t Scale,
687 int64_t BaseOffset, bool HasBaseReg,
1498 int64_t BaseOffset, bool HasBaseReg,
1524 bool HasBaseReg, int64_t Scale,
1850 bool HasBaseReg, int64_t Scale, unsigned AddrSpace, in isLegalAddressingMode() argument
1852 return Impl.isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale, in isLegalAddressingMode()
1910 int64_t BaseOffset, bool HasBaseReg, in getScalingFactorCost() argument
1913 return Impl.getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, Scale, in getScalingFactorCost()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h299 bool HasBaseReg, int64_t Scale,
304 AM.HasBaseReg = HasBaseReg;
334 int64_t BaseOffset, bool HasBaseReg, in getScalingFactorCost() argument
339 AM.HasBaseReg = HasBaseReg; in getScalingFactorCost()
H A DTargetLowering.h2332 bool HasBaseReg = false; member
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/
H A DTargetTransformInfo.cpp339 bool HasBaseReg, int64_t Scale, in isLegalAddressingMode() argument
342 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, in isLegalAddressingMode()
426 Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, in getScalingFactorCost() argument
429 Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace); in getScalingFactorCost()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUPerfHintAnalysis.cpp241 AM.HasBaseReg = !AM.BaseGV; in visit()
H A DSILoadStoreOptimizer.cpp1928 AM.HasBaseReg = true; in promoteConstantOffsetToImm()
1953 AM.HasBaseReg = true; in promoteConstantOffsetToImm()
H A DSIISelLowering.cpp1290 if (AM.HasBaseReg) { in isLegalMUBUFAddressingMode()
1348 if (AM.Scale == 1 && AM.HasBaseReg) in isLegalAddressingMode()
1367 if (AM.Scale == 1 && AM.HasBaseReg) in isLegalAddressingMode()
8840 AM.HasBaseReg = true; in performSHLPtrCombine()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp3507 !NewAddrMode.HasBaseReg); in addNewAddrMode()
4648 if (AddrMode.HasBaseReg) { in matchOperationAddr()
4653 AddrMode.HasBaseReg = true; in matchOperationAddr()
4664 if (AddrMode.HasBaseReg) in matchOperationAddr()
4666 AddrMode.HasBaseReg = true; in matchOperationAddr()
4801 if (!AddrMode.HasBaseReg) { in matchAddr()
4802 AddrMode.HasBaseReg = true; in matchAddr()
4807 AddrMode.HasBaseReg = false; in matchAddr()
H A DTargetLoweringBase.cpp1911 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
1916 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp853 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) { in isLegalAddressingMode()
865 if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 0 && isUInt<6>(Offs)) { in isLegalAddressingMode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp4209 return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale; in isLegalAddressingMode()
4216 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed. in isLegalAddressingMode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1891 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 && in isLegalAddressingMode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp17669 if (!AM.HasBaseReg && Scale == 2) in isLegalT2ScaledAddressingMode()
17695 return (Scale == 1) || (!AM.HasBaseReg && Scale == 2); in isLegalT1ScaledAddressingMode()
17742 if (Scale == 1 || (AM.HasBaseReg && Scale == -1)) in isLegalAddressingMode()
17745 if (!AM.HasBaseReg && Scale == 2) in isLegalAddressingMode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp4269 if (!AM.HasBaseReg) // allow "r+i". in isLegalAddressingMode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1036 AM.HasBaseReg = true; in reassociationCanBreakAddressingModePattern()
2075 AM.HasBaseReg = true; in canFoldInAddressingMode()
2084 AM.HasBaseReg = true; in canFoldInAddressingMode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp15831 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
15836 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp11718 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale) in isLegalAddressingMode()
11723 return AM.HasBaseReg && !AM.BaseOffs && !AM.Scale; in isLegalAddressingMode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp878 if (!AM.HasBaseReg) // allow "r+i". in isLegalAddressingMode()