| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 653 FSHR, enumerator
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 386 case ISD::FSHR: in LegalizeOp()
805 case ISD::FSHR: in Expand()
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| H A D | SelectionDAGDumper.cpp | 251 case ISD::FSHR: return "fshr"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 230 case ISD::FSHR: in PromoteIntegerResult()
1186 bool IsFSHR = Opcode == ISD::FSHR; in PromoteIntRes_FunnelShift()
2214 case ISD::FSHR: in ExpandIntegerResult()
3490 Lo = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 1], Result[Part0], in ExpandIntRes_MULFIX()
3492 Hi = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 2], Result[Part0 + 1], in ExpandIntRes_MULFIX()
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| H A D | LegalizeVectorTypes.cpp | 155 case ISD::FSHR: in ScalarizeVectorResult()
1050 case ISD::FSHR: in SplitVectorResult()
3154 case ISD::FSHR: in WidenVectorResult()
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| H A D | DAGCombiner.cpp | 1655 case ISD::FSHR: return visitFunnelShift(N); in visit()
6875 TLI.isOperationLegalOrCustom(ISD::FSHR, VT)) { in MatchFunnelPosNeg()
6876 return DAG.getNode(ISD::FSHR, DL, VT, N0.getOperand(0), N1, Neg); in MatchFunnelPosNeg()
6885 TLI.isOperationLegalOrCustom(ISD::FSHR, VT)) { in MatchFunnelPosNeg()
6886 return DAG.getNode(ISD::FSHR, DL, VT, N0.getOperand(0), N1, Neg); in MatchFunnelPosNeg()
6907 bool HasFSHR = hasOperation(ISD::FSHR, VT); in MatchRotate()
6993 Res = DAG.getNode(HasFSHL ? ISD::FSHL : ISD::FSHR, DL, VT, LHSShiftArg, in MatchRotate()
7054 LExtOp0, RExtOp0, ISD::FSHL, ISD::FSHR, DL); in MatchRotate()
7060 RExtOp0, LExtOp0, ISD::FSHR, ISD::FSHL, DL); in MatchRotate()
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| H A D | TargetLowering.cpp | 1679 case ISD::FSHR: { in SimplifyDemandedBits()
6480 unsigned RevOpcode = IsFSHL ? ISD::FSHR : ISD::FSHL; in expandFunnelShift()
6634 Tmp2 = DAG.getNode(ISD::FSHR, dl, VT, ShOpHi, ShOpLo, ShAmt); in expandShiftParts()
8159 SDValue Result = DAG.getNode(ISD::FSHR, dl, VT, Hi, Lo, in expandFixedPointMul()
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| H A D | LegalizeDAG.cpp | 1220 case ISD::FSHR: in LegalizeOp()
3362 case ISD::FSHR: in ExpandNode()
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| H A D | SelectionDAG.cpp | 3126 case ISD::FSHR: in computeKnownBits()
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| H A D | SelectionDAGBuilder.cpp | 6412 auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR; in visitIntrinsicCall()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 39 FSHR, enumerator
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| H A D | X86ISelLowering.cpp | 216 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) { in X86TargetLowering()
1756 setOperationAction(ISD::FSHR, VT, Custom); in X86TargetLowering()
19629 assert((Op.getOpcode() == ISD::FSHL || Op.getOpcode() == ISD::FSHR) && in LowerFunnelShift()
19637 bool IsFSHR = Op.getOpcode() == ISD::FSHR; in LowerFunnelShift()
19705 unsigned FSHOp = (IsFSHR ? X86ISD::FSHR : X86ISD::FSHL); in LowerFunnelShift()
28795 unsigned FunnelOpc = (Opcode == ISD::ROTL ? ISD::FSHL : ISD::FSHR); in LowerRotate()
30288 case ISD::FSHR: return LowerFunnelShift(Op, Subtarget, DAG); in LowerOperation()
31296 NODE_NAME_CASE(FSHR) in getTargetNodeName()
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| H A D | X86InstrInfo.td | 144 def X86fshr : SDNode<"X86ISD::FSHR", SDTIntShiftDOp>;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 755 setOperationAction(ISD::FSHR, VT, Expand); in initActions()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1580 setOperationAction(ISD::FSHR, MVT::i32, Legal); in HexagonTargetLowering()
1581 setOperationAction(ISD::FSHR, MVT::i64, Legal); in HexagonTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 287 setOperationAction(ISD::FSHR, XLenVT, Custom); in RISCVTargetLowering()
292 setOperationAction(ISD::FSHR, MVT::i32, Custom); in RISCVTargetLowering()
2006 case ISD::FSHR: { in LowerOperation()
4893 case ISD::FSHR: { in ReplaceNodeResults()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 386 def fshr : SDNode<"ISD::FSHR" , SDTIntShiftDOp>;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 702 setOperationAction(ISD::FSHR, MVT::i64, Custom); in PPCTargetLowering()
705 setOperationAction(ISD::FSHR, MVT::i32, Custom); in PPCTargetLowering()
10830 case ISD::FSHR: return LowerFunnelShift(Op, DAG); in LowerOperation()
10929 case ISD::FSHR: in ReplaceNodeResults()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 385 setOperationAction(ISD::FSHR, MVT::i32, Legal); in AMDGPUTargetLowering()
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| H A D | SIISelLowering.cpp | 6704 return DAG.getNode(ISD::FSHR, DL, VT, in LowerINTRINSIC_WO_CHAIN()
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