| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 652 FSHL, enumerator
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 385 case ISD::FSHL: in LegalizeOp()
804 case ISD::FSHL: in Expand()
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| H A D | SelectionDAGDumper.cpp | 250 case ISD::FSHL: return "fshl"; in getOperationName()
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| H A D | TargetLowering.cpp | 1678 case ISD::FSHL: in SimplifyDemandedBits()
1683 bool IsFSHL = (Op.getOpcode() == ISD::FSHL); in SimplifyDemandedBits()
6474 bool IsFSHL = Node->getOpcode() == ISD::FSHL; in expandFunnelShift()
6480 unsigned RevOpcode = IsFSHL ? ISD::FSHR : ISD::FSHL; in expandFunnelShift()
6631 Tmp2 = DAG.getNode(ISD::FSHL, dl, VT, ShOpHi, ShOpLo, ShAmt); in expandShiftParts()
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| H A D | LegalizeVectorTypes.cpp | 154 case ISD::FSHL: in ScalarizeVectorResult()
1049 case ISD::FSHL: in SplitVectorResult()
3153 case ISD::FSHL: in WidenVectorResult()
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| H A D | DAGCombiner.cpp | 1654 case ISD::FSHL: in visit()
6853 if (PosOpcode == ISD::FSHL && isPowerOf2_32(EltBits)) { in MatchFunnelPosNeg()
6866 TLI.isOperationLegalOrCustom(ISD::FSHL, VT)) { in MatchFunnelPosNeg()
6867 return DAG.getNode(ISD::FSHL, DL, VT, N0, N1.getOperand(0), Pos); in MatchFunnelPosNeg()
6906 bool HasFSHL = hasOperation(ISD::FSHL, VT); in MatchRotate()
6993 Res = DAG.getNode(HasFSHL ? ISD::FSHL : ISD::FSHR, DL, VT, LHSShiftArg, in MatchRotate()
7054 LExtOp0, RExtOp0, ISD::FSHL, ISD::FSHR, DL); in MatchRotate()
7060 RExtOp0, LExtOp0, ISD::FSHR, ISD::FSHL, DL); in MatchRotate()
8945 bool IsFSHL = N->getOpcode() == ISD::FSHL; in visitFunnelShift()
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| H A D | LegalizeDAG.cpp | 1219 case ISD::FSHL: in LegalizeOp()
3361 case ISD::FSHL: in ExpandNode()
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| H A D | LegalizeIntegerTypes.cpp | 229 case ISD::FSHL: in PromoteIntegerResult()
2213 case ISD::FSHL: in ExpandIntegerResult()
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| H A D | SelectionDAG.cpp | 3125 case ISD::FSHL: in computeKnownBits()
3133 Known = computeKnownBits(Op.getOperand(Opcode == ISD::FSHL ? 0 : 1), in computeKnownBits()
3142 if (Opcode == ISD::FSHL) { in computeKnownBits()
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| H A D | SelectionDAGBuilder.cpp | 6412 auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR; in visitIntrinsicCall()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 3041 { ISD::FSHL, MVT::i64, 4 } in getIntrinsicInstrCost()
3050 { ISD::FSHL, MVT::i32, 4 }, in getIntrinsicInstrCost()
3051 { ISD::FSHL, MVT::i16, 4 }, in getIntrinsicInstrCost()
3052 { ISD::FSHL, MVT::i8, 4 } in getIntrinsicInstrCost()
3063 ISD = ISD::FSHL; in getIntrinsicInstrCost()
3069 ISD = ISD::FSHL; in getIntrinsicInstrCost()
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| H A D | X86ISelLowering.h | 38 FSHL, enumerator
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| H A D | X86ISelLowering.cpp | 216 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) { in X86TargetLowering()
1755 setOperationAction(ISD::FSHL, VT, Custom); in X86TargetLowering()
19629 assert((Op.getOpcode() == ISD::FSHL || Op.getOpcode() == ISD::FSHR) && in LowerFunnelShift()
19705 unsigned FSHOp = (IsFSHR ? X86ISD::FSHR : X86ISD::FSHL); in LowerFunnelShift()
28795 unsigned FunnelOpc = (Opcode == ISD::ROTL ? ISD::FSHL : ISD::FSHR); in LowerRotate()
30287 case ISD::FSHL: in LowerOperation()
31295 NODE_NAME_CASE(FSHL) in getTargetNodeName()
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| H A D | X86InstrInfo.td | 143 def X86fshl : SDNode<"X86ISD::FSHL", SDTIntShiftDOp>;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 286 setOperationAction(ISD::FSHL, XLenVT, Custom); in RISCVTargetLowering()
291 setOperationAction(ISD::FSHL, MVT::i32, Custom); in RISCVTargetLowering()
2005 case ISD::FSHL: in LowerOperation()
2017 unsigned Opc = Op.getOpcode() == ISD::FSHL ? RISCVISD::FSL : RISCVISD::FSR; in LowerOperation()
4892 case ISD::FSHL: in ReplaceNodeResults()
4907 N->getOpcode() == ISD::FSHL ? RISCVISD::FSLW : RISCVISD::FSRW; in ReplaceNodeResults()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 754 setOperationAction(ISD::FSHL, VT, Expand); in initActions()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1578 setOperationAction(ISD::FSHL, MVT::i32, Legal); in HexagonTargetLowering()
1579 setOperationAction(ISD::FSHL, MVT::i64, Legal); in HexagonTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 385 def fshl : SDNode<"ISD::FSHL" , SDTIntShiftDOp>;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 701 setOperationAction(ISD::FSHL, MVT::i64, Custom); in PPCTargetLowering()
704 setOperationAction(ISD::FSHL, MVT::i32, Custom); in PPCTargetLowering()
8812 bool IsFSHL = Op.getOpcode() == ISD::FSHL; in LowerFunnelShift()
10829 case ISD::FSHL: return LowerFunnelShift(Op, DAG); in LowerOperation()
10928 case ISD::FSHL: in ReplaceNodeResults()
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