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Searched refs:FP_TO_SINT (Results 1 – 25 of 37) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp703 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 }, in getCastInstrCost()
704 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
705 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, in getCastInstrCost()
711 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 }, in getCastInstrCost()
712 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 }, in getCastInstrCost()
713 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 1 }, in getCastInstrCost()
719 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, in getCastInstrCost()
720 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 }, in getCastInstrCost()
725 { ISD::FP_TO_SINT, MVT::nxv2i64, MVT::nxv2f32, 1 }, in getCastInstrCost()
726 { ISD::FP_TO_SINT, MVT::nxv2i32, MVT::nxv2f32, 1 }, in getCastInstrCost()
[all …]
H A DAArch64ISelLowering.cpp443 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in AArch64TargetLowering()
444 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in AArch64TargetLowering()
445 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom); in AArch64TargetLowering()
885 setTargetDAGCombine(ISD::FP_TO_SINT); in AArch64TargetLowering()
983 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand); in AArch64TargetLowering()
1133 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in AArch64TargetLowering()
1405 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in addTypeForNEON()
4606 case ISD::FP_TO_SINT: in LowerOperation()
12454 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT; in performFpToIntCombine()
16092 case ISD::FP_TO_SINT: in PerformDAGCombine()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp627 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
629 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, in getCastInstrCost()
631 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, in getCastInstrCost()
645 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }, in getCastInstrCost()
647 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 }, in getCastInstrCost()
649 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 }, in getCastInstrCost()
662 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 }, in getCastInstrCost()
664 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 }, in getCastInstrCost()
666 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 }, in getCastInstrCost()
668 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 }, in getCastInstrCost()
[all …]
H A DARMISelLowering.cpp175 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in addTypeForNEON()
180 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addTypeForNEON()
310 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addMVEVectorTypes()
913 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom); in ARMTargetLowering()
914 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom); in ARMTargetLowering()
962 setTargetDAGCombine(ISD::FP_TO_SINT); in ARMTargetLowering()
1036 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in ARMTargetLowering()
1038 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom); in ARMTargetLowering()
5633 if (Op.getOpcode() == ISD::FP_TO_SINT || in LowerFP_TO_INT()
5653 DAG.getNode(Op.getOpcode() == ISD::STRICT_FP_TO_SINT ? ISD::FP_TO_SINT in LowerFP_TO_INT()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1535 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, in getCastInstrCost()
1536 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, in getCastInstrCost()
1648 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f64, 3 }, in getCastInstrCost()
1649 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, in getCastInstrCost()
1650 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 3 }, in getCastInstrCost()
1651 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 3 }, in getCastInstrCost()
1707 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, in getCastInstrCost()
1708 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, in getCastInstrCost()
1709 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, in getCastInstrCost()
1710 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, in getCastInstrCost()
[all …]
H A DREADME-FPStack.txt50 FP_TO_SINT when the source operand is already in memory.
H A DX86ISelLowering.cpp261 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); in X86TargetLowering()
264 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Custom); in X86TargetLowering()
266 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in X86TargetLowering()
270 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in X86TargetLowering()
848 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in X86TargetLowering()
1014 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); in X86TargetLowering()
1015 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom); in X86TargetLowering()
1021 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in X86TargetLowering()
1245 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v8i16, MVT::v8i32); in X86TargetLowering()
1249 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); in X86TargetLowering()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/
H A DConstrainedOps.def60 DAG_INSTRUCTION(FPToSI, 1, 0, experimental_constrained_fptosi, FP_TO_SINT)
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h775 FP_TO_SINT, enumerator
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp404 case ISD::FP_TO_SINT: in LegalizeOp()
583 case ISD::FP_TO_SINT: in Promote()
688 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) in PromoteFP_TO_INT()
689 NewOpc = ISD::FP_TO_SINT; in PromoteFP_TO_INT()
H A DLegalizeFloatTypes.cpp820 case ISD::FP_TO_SINT: in SoftenFloatOperand()
936 bool Signed = N->getOpcode() == ISD::FP_TO_SINT || in SoftenFloatOp_FP_TO_XINT()
1773 case ISD::FP_TO_SINT: in ExpandFloatOperand()
1905 bool Signed = N->getOpcode() == ISD::FP_TO_SINT || in ExpandFloatOp_FP_TO_XINT()
2082 case ISD::FP_TO_SINT: in PromoteFloatOperand()
2878 case ISD::FP_TO_SINT: in SoftPromoteHalfOperand()
H A DLegalizeDAG.cpp2576 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT || in PromoteLegalFP_TO_INT()
2592 OpToUse = IsStrict ? ISD::STRICT_FP_TO_SINT : ISD::FP_TO_SINT; in PromoteLegalFP_TO_INT()
2936 case ISD::FP_TO_SINT: in ExpandNode()
4203 case ISD::FP_TO_SINT: in ConvertNodeToLibcall()
4209 bool Signed = Node->getOpcode() == ISD::FP_TO_SINT || in ConvertNodeToLibcall()
4442 case ISD::FP_TO_SINT: in PromoteNode()
H A DSelectionDAGDumper.cpp350 case ISD::FP_TO_SINT: return "fp_to_sint"; in getOperationName()
H A DLegalizeVectorTypes.cpp94 case ISD::FP_TO_SINT: in ScalarizeVectorResult()
610 case ISD::FP_TO_SINT: in ScalarizeVectorOperand()
988 case ISD::FP_TO_SINT: in SplitVectorResult()
2195 case ISD::FP_TO_SINT: in SplitVectorOperand()
3091 case ISD::FP_TO_SINT: in WidenVectorResult()
4550 case ISD::FP_TO_SINT: in WidenVectorOperand()
H A DTargetLowering.cpp6742 ISD::FP_TO_SINT; in expandFP_TO_UINT()
6760 Result = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Src); in expandFP_TO_UINT()
6807 SInt = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Val); in expandFP_TO_UINT()
6816 SDValue True = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, Src); in expandFP_TO_UINT()
6818 SDValue False = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, in expandFP_TO_UINT()
8666 SDValue FpToInt = DAG.getNode(IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, in expandFP_TO_INT_SAT()
8687 DAG.getNode(IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, dl, DstVT, Src); in expandFP_TO_INT_SAT()
H A DLegalizeIntegerTypes.cpp128 case ISD::FP_TO_SINT: in PromoteIntegerResult()
596 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) in PromoteIntRes_FP_TO_XINT()
597 NewOpc = ISD::FP_TO_SINT; in PromoteIntRes_FP_TO_XINT()
2085 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; in ExpandIntegerResult()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp139 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Custom); in R600TargetLowering()
140 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in R600TargetLowering()
250 setTargetDAGCombine(ISD::FP_TO_SINT); in R600TargetLowering()
646 case ISD::FP_TO_SINT: { in ReplaceNodeResults()
1774 case ISD::FP_TO_SINT: { in PerformDAGCombine()
H A DAMDGPUISelLowering.cpp400 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in AMDGPUTargetLowering()
422 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in AMDGPUTargetLowering()
1260 case ISD::FP_TO_SINT: in LowerOperation()
1680 ISD::NodeType ToInt = Sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT; in LowerDIVREM24()
2604 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL, in LowerFP64_TO_INT()
2737 OpOpcode == ISD::FP_TO_SINT ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerFP_TO_INT()
2742 return LowerFP64_TO_INT(Op, DAG, OpOpcode == ISD::FP_TO_SINT); in LowerFP_TO_INT()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp250 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote); in PPCTargetLowering()
251 AddPromotedToType(ISD::FP_TO_SINT, MVT::i1, in PPCTargetLowering()
282 setOperationAction(ISD::FP_TO_SINT, MVT::ppcf128, Custom); in PPCTargetLowering()
484 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal); in PPCTargetLowering()
494 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
635 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
666 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
676 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
862 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); in PPCTargetLowering()
1050 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal); in PPCTargetLowering()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1512 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in SparcTargetLowering()
1514 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in SparcTargetLowering()
3026 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this, in LowerOperation()
3353 case ISD::FP_TO_SINT: in ReplaceNodeResults()
3359 libCall = ((N->getOpcode() == ISD::FP_TO_SINT) in ReplaceNodeResults()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp357 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in RISCVTargetLowering()
486 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in RISCVTargetLowering()
705 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in RISCVTargetLowering()
2180 case ISD::FP_TO_SINT: in LowerOperation()
2251 case ISD::FP_TO_SINT: in LowerOperation()
4627 case ISD::FP_TO_SINT: in ReplaceNodeResults()
4641 if (N->getOpcode() == ISD::FP_TO_SINT || in ReplaceNodeResults()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp358 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in MipsTargetLowering()
374 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in MipsTargetLowering()
1232 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); in LowerOperation()
2779 if (Val.getOpcode() != ISD::FP_TO_SINT || in lowerFP_TO_SINT_STORE()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1767 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote); in HexagonTargetLowering()
1768 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); in HexagonTargetLowering()
1769 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); in HexagonTargetLowering()
/netbsd-src/external/apache2/llvm/dist/llvm/docs/
H A DWritingAnLLVMBackend.rst1432 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1436 code, an ``FP_TO_SINT`` opcode will call the ``LowerFP_TO_SINT`` method:
1442 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1784 case FPToSI: return ISD::FP_TO_SINT; in InstructionOpcodeToISD()

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