| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 484 setOperationAction(ISD::FNEG, VT, Expand); in AMDGPUTargetLowering()
561 setTargetDAGCombine(ISD::FNEG); in AMDGPUTargetLowering()
1715 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq); in LowerDIVREM24()
2107 SDValue Neg = DAG.getNode(ISD::FNEG, SL, VT, Trunc, Flags); in LowerFREM()
2480 SDValue RNeg = DAG.getNode(ISD::FNEG, SL, MVT::f32, R); in LowerINT_TO_FP32()
3505 (LHS.getOpcode() == ISD::FNEG && RHS.getOpcode() == ISD::FNEG)) { in foldFreeOpFromSelect()
3511 if (RHS.getOpcode() == ISD::FABS || RHS.getOpcode() == ISD::FNEG) { in foldFreeOpFromSelect()
3518 if ((LHS.getOpcode() == ISD::FNEG || LHS.getOpcode() == ISD::FABS) && CRHS) { in foldFreeOpFromSelect()
3530 if (LHS.getOpcode() == ISD::FNEG && fnegFoldsIntoOp(Opc)) in foldFreeOpFromSelect()
3537 if (LHS.getOpcode() == ISD::FNEG) in foldFreeOpFromSelect()
[all …]
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| H A D | AMDGPUISelDAGToDAG.cpp | 2668 if (Src.getOpcode() == ISD::FNEG) { in SelectVOP3ModsImpl()
2710 if (In.getOpcode() == ISD::FABS || In.getOpcode() == ISD::FNEG) in SelectVOP3NoMods()
2753 if (Src.getOpcode() == ISD::FNEG) { in SelectVOP3PMods()
2764 if (Lo.getOpcode() == ISD::FNEG) { in SelectVOP3PMods()
2769 if (Hi.getOpcode() == ISD::FNEG) { in SelectVOP3PMods()
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| H A D | R600Instructions.td | 700 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
703 "FNEG $dst, $src0",
1220 def FNEG_R600 : FNEG<R600_Reg32>;
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| H A D | SIISelLowering.cpp | 647 setOperationAction(ISD::FNEG, MVT::v2f16, Legal); in SITargetLowering()
732 setOperationAction(ISD::FNEG, MVT::v2f32, Legal); in SITargetLowering()
742 setOperationAction(ISD::FNEG, MVT::v4f16, Custom); in SITargetLowering()
755 setOperationAction(ISD::FNEG, MVT::v2f16, Custom); in SITargetLowering()
4521 case ISD::FNEG: in LowerOperation()
4872 case ISD::FNEG: { in ReplaceNodeResults()
8262 SDValue FNegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in lowerFastUnsafeFDIV()
8286 SDValue NegY = DAG.getNode(ISD::FNEG, SL, VT, Y); in lowerFastUnsafeFDIV64()
8438 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f32, in LowerFDIV32()
8541 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f64, DivScale0); in LowerFDIV64()
[all …]
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| H A D | AMDGPUTargetTransformInfo.cpp | 703 case ISD::FNEG: in getArithmeticInstrCost()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 856 FNEG, enumerator
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| /netbsd-src/sys/arch/m68k/fpsp/ |
| H A D | satanh.sa | 106 FNEG.X FP1 ...-Y
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| H A D | sacos.sa | 103 FNEG.X FP0 ... -X
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 1697 case ISD::FNEG: return visitFNEG(N); in visit()
12400 FPOpcode = ISD::FNEG; in foldBitcastedFPLogic()
12423 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, FPOp); in foldBitcastedFPLogic()
12513 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) || in visitBITCAST()
12526 if (N0.getOpcode() == ISD::FNEG) { in visitBITCAST()
12545 if (N0.getOpcode() == ISD::FNEG) in visitBITCAST()
13076 XY.getOperand(1), DAG.getNode(ISD::FNEG, SL, VT, Z)); in visitFSUBForFMACombine()
13086 DAG.getNode(ISD::FNEG, SL, VT, YZ.getOperand(0)), in visitFSUBForFMACombine()
13112 if (N0.getOpcode() == ISD::FNEG && isContractableFMUL(N0.getOperand(0)) && in visitFSUBForFMACombine()
13117 DAG.getNode(ISD::FNEG, SL, VT, N00), N01, in visitFSUBForFMACombine()
[all …]
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| H A D | LegalizeFloatTypes.cpp | 100 case ISD::FNEG: R = SoftenFloatRes_FNEG(N); break; in SoftenFloatResult()
1219 case ISD::FNEG: ExpandFloatRes_FNEG(N, Lo, Hi); break; in ExpandFloatResult()
1310 DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo), in ExpandFloatRes_FABS()
1475 Lo = DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo); in ExpandFloatRes_FNEG()
1476 Hi = DAG.getNode(ISD::FNEG, dl, Hi.getValueType(), Hi); in ExpandFloatRes_FNEG()
2237 case ISD::FNEG: in PromoteFloatResult()
2601 case ISD::FNEG: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorOps.cpp | 406 case ISD::FNEG: in LegalizeOp()
766 case ISD::FNEG: in Expand()
1342 if (TLI.isOperationLegalOrCustom(ISD::FNEG, VT) && in ExpandFSUB()
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| H A D | SelectionDAGBuilder.h | 685 void visitFNeg(const User &I) { visitUnary(I, ISD::FNEG); } in visitFNeg()
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| H A D | LegalizeDAG.cpp | 1567 TLI.isOperationLegalOrCustom(ISD::FNEG, FloatVT)) { in ExpandFCOPYSIGN()
1569 SDValue NegValue = DAG.getNode(ISD::FNEG, DL, FloatVT, AbsValue); in ExpandFCOPYSIGN()
3123 case ISD::FNEG: in ExpandNode()
3232 TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) { in ExpandNode()
3234 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1)); in ExpandNode()
3819 SDValue Neg = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(2), Flags); in ExpandNode()
4734 case ISD::FNEG: in PromoteNode()
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| H A D | SelectionDAGDumper.cpp | 194 case ISD::FNEG: return "fneg"; in getOperationName()
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| /netbsd-src/sys/arch/m68k/m68k/ |
| H A D | db_disasm.h | 365 #define FNEG ENCFT(0,1,1,0,1,0) macro
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| /netbsd-src/sys/arch/sparc/include/ |
| H A D | instr.h | 407 #define FNEG 0x04 macro
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 617 { ISD::FNEG, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
622 { ISD::FNEG, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
788 { ISD::FNEG, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
789 { ISD::FNEG, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
829 { ISD::FNEG, MVT::v4f64, 2 }, // BTVER2 from http://www.agner.org/ in getArithmeticInstrCost()
830 { ISD::FNEG, MVT::v8f32, 2 }, // BTVER2 from http://www.agner.org/ in getArithmeticInstrCost()
935 { ISD::FNEG, MVT::f32, 1 }, // Pentium IV from http://www.agner.org/ in getArithmeticInstrCost()
936 { ISD::FNEG, MVT::f64, 1 }, // Pentium IV from http://www.agner.org/ in getArithmeticInstrCost()
937 { ISD::FNEG, MVT::v4f32, 1 }, // Pentium IV from http://www.agner.org/ in getArithmeticInstrCost()
938 { ISD::FNEG, MVT::v2f64, 1 }, // Pentium IV from http://www.agner.org/ in getArithmeticInstrCost()
[all …]
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| /netbsd-src/sys/arch/m68k/fpe/ |
| H A D | README | 67 Type=0: FMOVE (mem->FPr), FINT, FINTRZ, FSQRT, FABS, FNEG, FGETEXP,
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| /netbsd-src/sys/arch/sparc/fpu/ |
| H A D | fpu.c | 465 case FNEG >> 2: in fpu_execute()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1621 setOperationAction(ISD::FNEG, MVT::f64, Custom); in SparcTargetLowering()
1728 setOperationAction(ISD::FNEG, MVT::f128, Legal); in SparcTargetLowering()
1731 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
1750 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
2702 assert(opcode == ISD::FNEG || opcode == ISD::FABS); in LowerF64Op()
2846 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS) in LowerFNEGorFABS()
3056 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9); in LowerOperation()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedFalkorDetails.td | 586 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(FABS|FNEG)v2f32$")>;
612 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(FABS|FNEG)(v2f64|v4f32)$")>;
1117 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(FABS|FNEG)(S|D)r$")>;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MicroMipsInstrFPU.td | 161 defm FNEG : ABSS_MMM<"neg.d", II_NEG, fneg>, ABS_FM_MM<1, 0x2d>;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | P9InstrResources.td | 188 (instregex "FNEG(D|S)$"),
1057 (instregex "FNEG(D|S)_rec$"),
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| /netbsd-src/sys/external/bsd/sljit/dist/sljit_src/ |
| H A D | sljitNativeARM_64.c | 92 #define FNEG 0x1e614000 macro
1714 FAIL_IF(push_inst(compiler, (FNEG ^ inv_bits) | VD(dst_r) | VN(src))); in sljit_emit_fop1()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 763 setOperationAction(ISD::FNEG, VT, Custom); in RISCVTargetLowering()
2380 case ISD::FNEG: in LowerOperation()
5545 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) || in PerformDAGCombine()
5554 if (Op0.getOpcode() == ISD::FNEG) { in PerformDAGCombine()
5719 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) || in PerformDAGCombine()
5725 if (Op0.getOpcode() == ISD::FNEG) in PerformDAGCombine()
5863 if (In2.getOpcode() != ISD::FNEG) in PerformDAGCombine()
5868 DAG.getNode(ISD::FNEG, DL, VT, NewFPExtRound)); in PerformDAGCombine()
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