| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 470 FCOPYSIGN, enumerator
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| H A D | BasicTTIImpl.h | 1568 ISDs.push_back(ISD::FCOPYSIGN); in getTypeBasedIntrinsicInstrCost()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeFloatTypes.cpp | 77 case ISD::FCOPYSIGN: R = SoftenFloatRes_FCOPYSIGN(N); break; in SoftenFloatResult()
838 case ISD::FCOPYSIGN: Res = SoftenFloatOp_FCOPYSIGN(N); break; in SoftenFloatOperand()
1085 return DAG.getNode(ISD::FCOPYSIGN, dl, LVT, LHS, RHS); in SoftenFloatOp_FCOPYSIGN()
1196 case ISD::FCOPYSIGN: ExpandFloatRes_FCOPYSIGN(N, Lo, Hi); break; in ExpandFloatResult()
1768 case ISD::FCOPYSIGN: Res = ExpandFloatOp_FCOPYSIGN(N); break; in ExpandFloatOperand()
1867 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), in ExpandFloatOp_FCOPYSIGN()
2081 case ISD::FCOPYSIGN: R = PromoteFloatOp_FCOPYSIGN(N, OpNo); break; in PromoteFloatOperand()
2223 case ISD::FCOPYSIGN: R = PromoteFloatRes_FCOPYSIGN(N); break; in PromoteFloatResult()
2585 case ISD::FCOPYSIGN: R = SoftPromoteHalfRes_FCOPYSIGN(N); break; in SoftPromoteHalfResult()
2877 case ISD::FCOPYSIGN: Res = SoftPromoteHalfOp_FCOPYSIGN(N, OpNo); break; in SoftPromoteHalfOperand()
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| H A D | LegalizeVectorTypes.cpp | 114 case ISD::FCOPYSIGN: in ScalarizeVectorResult()
925 case ISD::FCOPYSIGN: SplitVecRes_FCOPYSIGN(N, Lo, Hi); break; in SplitVectorResult()
1356 Lo = DAG.getNode(ISD::FCOPYSIGN, DL, LHSLo.getValueType(), LHSLo, RHSLo); in SplitVecRes_FCOPYSIGN()
1357 Hi = DAG.getNode(ISD::FCOPYSIGN, DL, LHSHi.getValueType(), LHSHi, RHSHi); in SplitVecRes_FCOPYSIGN()
2165 case ISD::FCOPYSIGN: Res = SplitVecOp_FCOPYSIGN(N); break; in SplitVectorOperand()
3074 case ISD::FCOPYSIGN: in WidenVectorResult()
4538 case ISD::FCOPYSIGN: Res = WidenVecOp_FCOPYSIGN(N); break; in WidenVectorOperand()
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| H A D | SelectionDAGDumper.cpp | 265 case ISD::FCOPYSIGN: return "fcopysign"; in getOperationName()
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| H A D | LegalizeDAG.cpp | 1630 if (TLI.isOperationLegalOrCustom(ISD::FCOPYSIGN, FloatVT)) { in ExpandFABS()
1632 return DAG.getNode(ISD::FCOPYSIGN, DL, FloatVT, Value, Zero); in ExpandFABS()
3120 case ISD::FCOPYSIGN: in ExpandNode()
4711 case ISD::FCOPYSIGN: in PromoteNode()
4722 const bool isTrunc = (Node->getOpcode() == ISD::FCOPYSIGN); in PromoteNode()
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| H A D | LegalizeVectorOps.cpp | 414 case ISD::FCOPYSIGN: in LegalizeOp()
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| H A D | DAGCombiner.cpp | 1689 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); in visit()
12564 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && in visitBITCAST()
14276 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1); in visitFCOPYSIGN()
14296 N0.getOpcode() == ISD::FCOPYSIGN) in visitFCOPYSIGN()
14297 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0.getOperand(0), N1); in visitFCOPYSIGN()
14304 if (N1.getOpcode() == ISD::FCOPYSIGN) in visitFCOPYSIGN()
14305 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1.getOperand(1)); in visitFCOPYSIGN()
14310 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1.getOperand(0)); in visitFCOPYSIGN()
14632 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { in visitFP_ROUND()
14636 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, in visitFP_ROUND()
[all …]
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| H A D | SelectionDAG.cpp | 4311 case ISD::FCOPYSIGN: { in isKnownNeverNaN()
5407 case ISD::FCOPYSIGN: in foldConstantFPMath()
5611 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match. in getNode()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Support/ |
| H A D | TargetOpcodes.def | 606 /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This does
608 /// floating point. X and the result must have the same type. FCOPYSIGN(f32,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 548 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand); in NVPTXTargetLowering()
549 setOperationAction(ISD::FCOPYSIGN, MVT::v2f16, Expand); in NVPTXTargetLowering()
550 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in NVPTXTargetLowering()
551 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in NVPTXTargetLowering()
2142 RoundedA = DAG.getNode(ISD::FCOPYSIGN, SL, VT, RoundedA, A); in LowerFROUND64()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 207 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in R600TargetLowering()
208 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in R600TargetLowering()
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| H A D | AMDGPUISelLowering.cpp | 487 setOperationAction(ISD::FCOPYSIGN, VT, Expand); in AMDGPUTargetLowering()
2209 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src); in LowerFRINT()
2257 SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, VT, One, X); in LowerFROUND()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1645 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); in SparcTargetLowering()
1646 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in SparcTargetLowering()
1647 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in SparcTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 574 setOperationAction(ISD::FCOPYSIGN, VT, Legal); in RISCVTargetLowering()
765 setOperationAction(ISD::FCOPYSIGN, VT, Custom); in RISCVTargetLowering()
817 setTargetDAGCombine(ISD::FCOPYSIGN); in RISCVTargetLowering()
2404 case ISD::FCOPYSIGN: in LowerOperation()
5846 case ISD::FCOPYSIGN: { in PerformDAGCombine()
5867 return DAG.getNode(ISD::FCOPYSIGN, DL, VT, N->getOperand(0), in PerformDAGCombine()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 419 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); in AArch64TargetLowering()
566 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); in AArch64TargetLowering()
567 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); in AArch64TargetLowering()
569 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Custom); in AArch64TargetLowering()
571 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote); in AArch64TargetLowering()
652 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand); in AArch64TargetLowering()
662 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand); in AArch64TargetLowering()
959 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand); in AArch64TargetLowering()
1374 setOperationAction(ISD::FCOPYSIGN, VT, Custom); in addTypeForNEON()
4593 case ISD::FCOPYSIGN: in LowerOperation()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 356 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); in MipsTargetLowering()
357 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); in MipsTargetLowering()
1220 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); in LowerOperation()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 808 setOperationAction(ISD::FCOPYSIGN, VT, Expand); in initActions()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 400 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal); in PPCTargetLowering()
401 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal); in PPCTargetLowering()
403 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in PPCTargetLowering()
404 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in PPCTargetLowering()
1077 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal); in PPCTargetLowering()
1078 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Legal); in PPCTargetLowering()
1215 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); in PPCTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 210 for (auto Op : {ISD::FCOPYSIGN, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, in WebAssemblyTargetLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 241 setOperationAction(ISD::FCOPYSIGN, VT, Expand); in initSPUActions()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 498 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 833 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand); in ARMTargetLowering()
1016 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in ARMTargetLowering()
1394 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); in ARMTargetLowering()
1395 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); in ARMTargetLowering()
1467 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand); in ARMTargetLowering()
9866 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); in LowerOperation()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 574 setOperationAction(ISD::FCOPYSIGN, VT, Custom); in X86TargetLowering()
609 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in X86TargetLowering()
610 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); in X86TargetLowering()
631 setOperationAction(ISD::FCOPYSIGN, VT, Expand); in X86TargetLowering()
683 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); in X86TargetLowering()
747 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Custom); in X86TargetLowering()
807 setOperationAction(ISD::FCOPYSIGN, VT, Expand); in X86TargetLowering()
890 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Custom); in X86TargetLowering()
950 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Custom); in X86TargetLowering()
1240 setOperationAction(ISD::FCOPYSIGN, VT, Custom); in X86TargetLowering()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1594 ISD::FPOW, ISD::FCOPYSIGN}) { in HexagonTargetLowering()
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