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Searched refs:EXTRACT_SUBVECTOR (Results 1 – 23 of 23) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp54 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; in ScalarizeVectorResult()
922 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break; in SplitVectorResult()
1262 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); in SplitVecRes_EXTRACT_SUBVECTOR()
1265 ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, in SplitVecRes_EXTRACT_SUBVECTOR()
2156 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; in SplitVectorOperand()
2425 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx); in SplitVecOp_EXTRACT_SUBVECTOR()
2427 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi, in SplitVecOp_EXTRACT_SUBVECTOR()
2984 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break; in WidenVectorResult()
3316 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1, in WidenVecRes_BinaryCanTrap()
3318 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2, in WidenVecRes_BinaryCanTrap()
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H A DDAGCombiner.cpp655 case ISD::EXTRACT_SUBVECTOR: in getStoreSource()
1714 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); in visit()
12272 if (!LegalTypes && N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) { in visitTRUNCATE()
12279 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N0->getOperand(0)), VT, in visitTRUNCATE()
16788 Val.getOpcode() == ISD::EXTRACT_SUBVECTOR)) { in mergeStoresOfConstantsOrVecElts()
16794 unsigned OpC = MemVT.isVector() ? ISD::EXTRACT_SUBVECTOR in mergeStoresOfConstantsOrVecElts()
16962 OtherBC.getOpcode() != ISD::EXTRACT_SUBVECTOR) in getStoreMergeCandidates()
19052 VecIn2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, VecIn1, in createBuildVecShuffle()
19054 VecIn1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, VecIn1, ZeroIdx); in createBuildVecShuffle()
19124 Shuffle = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Shuffle, ZeroIdx); in createBuildVecShuffle()
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H A DSelectionDAG.cpp2550 case ISD::EXTRACT_SUBVECTOR: { in isSplatValue()
2898 case ISD::EXTRACT_SUBVECTOR: { in computeKnownBits()
4094 case ISD::EXTRACT_SUBVECTOR: { in ComputeNumSignBits()
4511 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR || in foldCONCAT_VECTORS()
5808 if (N1.getOpcode() == ISD::EXTRACT_SUBVECTOR && in getNode()
5836 case ISD::EXTRACT_SUBVECTOR: in getNode()
6087 if (N1.isUndef() && N2.getOpcode() == ISD::EXTRACT_SUBVECTOR && in getNode()
9475 while (V.getOpcode() == ISD::EXTRACT_SUBVECTOR) in peekThroughExtractSubvectors()
9843 return getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(Op), SubVT, Op, in matchBinOpReduction()
9898 if (Op0.getOpcode() != ISD::EXTRACT_SUBVECTOR || in matchBinOpReduction()
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H A DSelectionDAGDumper.cpp288 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; in getOperationName()
H A DLegalizeIntegerTypes.cpp97 case ISD::EXTRACT_SUBVECTOR: in PromoteIntegerResult()
426 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, InOp, in PromoteIntRes_BITCAST()
1273 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, WideExt, ZeroIdx); in PromoteIntRes_TRUNCATE()
1521 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break; in PromoteIntegerOperand()
4668 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), ExtVT, Ops); in PromoteIntRes_EXTRACT_SUBVECTOR()
4912 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, N->getOperand(1)); in PromoteIntOp_EXTRACT_SUBVECTOR()
H A DSelectionDAGBuilder.cpp412 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, in getCopyFromPartsVector()
750 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val, in getCopyToPartsVector()
3652 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Result, in visitShuffleVector()
3697 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Src, in visitShuffleVector()
7145 setValue(&I, DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ResultVT, Vec, Index)); in visitIntrinsicCall()
H A DTargetLowering.cpp1084 case ISD::EXTRACT_SUBVECTOR: { in SimplifyDemandedBits()
2616 case ISD::EXTRACT_SUBVECTOR: { in SimplifyDemandedVectorElts()
H A DLegalizeDAG.cpp2981 case ISD::EXTRACT_SUBVECTOR: in ExpandNode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp330 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom); in AMDGPUTargetLowering()
331 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom); in AMDGPUTargetLowering()
332 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3f32, Custom); in AMDGPUTargetLowering()
333 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3i32, Custom); in AMDGPUTargetLowering()
334 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom); in AMDGPUTargetLowering()
335 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom); in AMDGPUTargetLowering()
336 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5f32, Custom); in AMDGPUTargetLowering()
337 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5i32, Custom); in AMDGPUTargetLowering()
338 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom); in AMDGPUTargetLowering()
339 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom); in AMDGPUTargetLowering()
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H A DSIISelLowering.cpp258 case ISD::EXTRACT_SUBVECTOR: in SITargetLowering()
581 case ISD::EXTRACT_SUBVECTOR: in SITargetLowering()
1649 Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, NarrowedVT, Val, in convertArgType()
5540 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, in lowerVECTOR_SHUFFLE()
5868 Data = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MaskPopVT, in constructRetValue()
6336 auto Subvector = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, WidenedOp, in lowerSBuffer()
7450 auto Extract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, NewOp, in getMemIntrinsicNode()
9610 case ISD::EXTRACT_SUBVECTOR: { in isCanonicalized()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h543 EXTRACT_SUBVECTOR, enumerator
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp155 setTargetDAGCombine(ISD::EXTRACT_SUBVECTOR); in WebAssemblyTargetLowering()
2088 if (Extract.getOpcode() != ISD::EXTRACT_SUBVECTOR) in performVectorExtendCombine()
2143 if (Extract.getOpcode() != ISD::EXTRACT_SUBVECTOR) in performVectorConvertLowCombine()
2160 } else if (N->getOpcode() == ISD::EXTRACT_SUBVECTOR) { in performVectorConvertLowCombine()
2247 case ISD::EXTRACT_SUBVECTOR: in PerformDAGCombine()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp826 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand); in X86TargetLowering()
1410 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); in X86TargetLowering()
1506 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in X86TargetLowering()
1720 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); in X86TargetLowering()
1881 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in X86TargetLowering()
2011 setTargetDAGCombine(ISD::EXTRACT_SUBVECTOR); in X86TargetLowering()
4916 if (Opcode == ISD::EXTRACT_SUBVECTOR) in isTargetShuffleSplat()
5259 if (UI->getOpcode() != ISD::EXTRACT_SUBVECTOR || !UI->hasOneUse() || in shouldReduceLoadWidth()
5331 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
5907 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx); in extractSubVector()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp123 setOperationAction(ISD::EXTRACT_SUBVECTOR, T, Custom); in initializeHVXLowering()
227 setOperationAction(ISD::EXTRACT_SUBVECTOR, BoolV, Custom); in initializeHVXLowering()
1968 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, RetTy, in WidenHvxSetCC()
2050 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResTy, in WidenHvxTruncate()
2104 case ISD::EXTRACT_SUBVECTOR: return LowerHvxExtractSubvector(Op, DAG); in LowerHvxOperation()
H A DHexagonISelLowering.cpp1648 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, in HexagonTargetLowering()
1697 setOperationAction(ISD::EXTRACT_SUBVECTOR, NativeVT, Custom); in HexagonTargetLowering()
3140 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); in LowerOperation()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1170 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1381 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in addTypeForNEON()
1441 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in addTypeForFixedLengthSVE()
4407 DAG.getNode(ISD::EXTRACT_SUBVECTOR, Dl, in LowerSTORE()
4411 DAG.getNode(ISD::EXTRACT_SUBVECTOR, Dl, in LowerSTORE()
4564 case ISD::EXTRACT_SUBVECTOR: in LowerOperation()
8309 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8315 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8320 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8323 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
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H A DAArch64ISelDAGToDAG.cpp612 if (EV.getOpcode() != ISD::EXTRACT_SUBVECTOR) in checkHighLaneIndex()
2039 if (Extract.getOpcode() != ISD::EXTRACT_SUBVECTOR) in tryHighFPExt()
3439 case ISD::EXTRACT_SUBVECTOR: { in Select()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp441 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
522 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
586 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
635 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
746 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
1272 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V, Zero); in convertFromScalableVector()
1421 Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Vec, in lowerBUILD_VECTOR()
2302 case ISD::EXTRACT_SUBVECTOR: in LowerOperation()
3781 AlignedExtract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InterSubVT, Vec, in lowerINSERT_SUBVECTOR()
3856 Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ExtSubVecVT, Vec, in lowerEXTRACT_SUBVECTOR()
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H A DRISCVISelDAGToDAG.cpp1096 case ISD::EXTRACT_SUBVECTOR: { in Select()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp186 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); in addTypeForNEON()
441 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in addMVEVectorTypes()
5930 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast, in CombineVMOVDRRCandidateWithVecOp()
7834 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
7840 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
7845 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
7848 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
9144 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
9146 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerSDIV()
9148 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td683 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
688 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2167 case ISD::EXTRACT_SUBVECTOR: in LowerOperation()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp7756 Op1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, N1, in LowerTRUNCATEVector()
7758 Op2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, N1, in LowerTRUNCATEVector()
10718 case ISD::EXTRACT_SUBVECTOR: { in LowerFP_EXTEND()