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Searched refs:DPR (Results 1 – 13 of 13) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMInstrNEON.td128 def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
146 def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> {
155 def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
173 def VecListThreeQ : RegisterOperand<DPR, "printVectorListThreeSpaced"> {
182 def VecListFourQ : RegisterOperand<DPR, "printVectorListFourSpaced"> {
192 def VecListOneDAllLanes : RegisterOperand<DPR, "printVectorListOneAllLanes"> {
221 def VecListThreeDAllLanes : RegisterOperand<DPR,
231 def VecListThreeQAllLanes : RegisterOperand<DPR,
241 def VecListFourDAllLanes : RegisterOperand<DPR, "printVectorListFourAllLanes"> {
250 def VecListFourQAllLanes : RegisterOperand<DPR,
[all …]
H A DARMInstrVFP.td154 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
156 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>,
189 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
191 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>,
405 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
407 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>,
430 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
432 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>,
455 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
457 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>,
[all …]
H A DARMRegisterInfo.td432 def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16, v4bf16], 64,
436 let AltOrders = [(rotl DPR, 16),
437 (add (decimate (rotl DPR, 16), 2), (rotl DPR, 16))];
441 let DiagnosticType = "DPR";
447 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
451 // Subset of DPR that are accessible with VFP2 (and so that also have
454 (trunc DPR, 16)> {
458 // Subset of DPR which can be used as a source of NEON scalars for 16-bit
461 (trunc DPR, 8)> {
499 [(decimate (shl DPR, 1), 2),
[all …]
H A DARMInstrCDE.td554 def : Pat<(f64 (int_arm_cde_vcx1a timm:$coproc, (f64 DPR:$acc), timm:$imm)),
555 (f64 (CDE_VCX1A_fpdp p_imm:$coproc, DPR:$acc, imm_11b:$imm))>;
562 def : Pat<(f64 (int_arm_cde_vcx2 timm:$coproc, (f64 DPR:$n), timm:$imm)),
563 (f64 (CDE_VCX2_fpdp p_imm:$coproc, DPR:$n, imm_6b:$imm))>;
564 def : Pat<(f64 (int_arm_cde_vcx2a timm:$coproc, (f64 DPR:$acc), (f64 DPR:$n),
566 (f64 (CDE_VCX2A_fpdp p_imm:$coproc, DPR:$acc, DPR:$n, imm_6b:$imm))>;
576 def : Pat<(f64 (int_arm_cde_vcx3 timm:$coproc, (f64 DPR:$n), (f64 DPR:$m),
578 (f64 (CDE_VCX3_fpdp p_imm:$coproc, DPR:$n, DPR:$m, imm_3b:$imm))>;
579 def : Pat<(f64 (int_arm_cde_vcx3a timm:$coproc, (f64 DPR:$acc), (f64 DPR:$n),
580 (f64 DPR:$m), timm:$imm)),
[all …]
H A DARMRegisterBanks.td13 def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;
H A DREADME.txt170 before the call and place the result in a callee-save DPR register. The two
H A DARMInstrMVE.td1847 def : Pat<(insertelt (v2f64 MQPR:$src1), DPR:$src2, imm:$lane),
1848 …(INSERT_SUBREG (v2f64 (COPY_TO_REGCLASS MQPR:$src1, MQPR)), DPR:$src2, (DSubReg_f64_reg imm:$lane)…
1917 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
1918 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
/netbsd-src/sys/dev/pci/
H A Dahc_pci.c701 #define DPR 0x01 macro
1442 if (status1 & DPR) { in ahc_pci_intr()
1451 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { in ahc_pci_intr()
H A Dahd_pci.c903 #define DPR 0x01 macro
/netbsd-src/sys/dev/pci/bktr/
H A Dbktr_os.c168 #define DPR(x) (bktr_debug ? printf x : (void)0) macro
170 #define DPR(x) macro
1487 DPR(("pci_mapreg_map: size %lx\n", in bktr_attach()
/netbsd-src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/marvell/
H A Darmada-8040-db.dts268 * Proper NAND usage will require DPR-76 to be in position 1-2, which disables
/netbsd-src/sys/dev/microcode/aic7xxx/
H A Daic79xx.reg1105 field DPR 0x01
1122 field DPR 0x01
1138 field DPR 0x01
1155 field DPR 0x01
1171 field DPR 0x01
1186 field DPR 0x01
H A Daic79xx_reg.h3276 #define DPR 0x01 macro