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Searched refs:CSR_READ_4 (Results 1 – 25 of 47) sorted by relevance

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/netbsd-src/sys/dev/pci/
H A Dif_alc.c222 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_readreg_813x()
254 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_readreg_816x()
294 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_writereg_813x()
323 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_writereg_816x()
371 reg = CSR_READ_4(sc, ALC_MAC_CFG); in alc_miibus_statchg()
425 v = CSR_READ_4(sc, ALC_MDIO); in alc_miiext_readreg()
457 v = CSR_READ_4(sc, ALC_MDIO); in alc_miiext_writereg()
619 opt = CSR_READ_4(sc, ALC_OPT_CFG); in alc_get_macaddr_813x()
620 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && in alc_get_macaddr_813x()
621 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { in alc_get_macaddr_813x()
[all …]
H A Dif_bge.c955 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) in bge_nvram_getbyte()
963 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); in bge_nvram_getbyte()
970 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { in bge_nvram_getbyte()
982 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); in bge_nvram_getbyte()
1046 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) in bge_eeprom_getbyte()
1056 byte = CSR_READ_4(sc, BGE_EE_DATA); in bge_eeprom_getbyte()
1098 autopoll = CSR_READ_4(sc, BGE_MI_MODE); in bge_miibus_readreg()
1110 data = CSR_READ_4(sc, BGE_MI_COMM); in bge_miibus_readreg()
1113 data = CSR_READ_4(sc, BGE_MI_COMM); in bge_miibus_readreg()
1157 autopoll = CSR_READ_4(s in bge_miibus_writereg()
[all...]
H A Dif_ale.c155 v = CSR_READ_4(sc, ALE_MDIO); in ale_miibus_readreg()
196 v = CSR_READ_4(sc, ALE_MDIO); in ale_miibus_writereg()
246 reg = CSR_READ_4(sc, ALE_MAC_CFG); in ale_miibus_statchg()
296 reg = CSR_READ_4(sc, ALE_SPI_CTRL); in ale_get_macaddr()
308 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | in ale_get_macaddr()
312 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); in ale_get_macaddr()
325 ea[0] = CSR_READ_4(sc, ALE_PAR0); in ale_get_macaddr()
326 ea[1] = CSR_READ_4(sc, ALE_PAR1); in ale_get_macaddr()
461 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { in ale_attach()
493 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> in ale_attach()
[all …]
H A Dif_age.c214 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> in age_attach()
222 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), in age_attach()
223 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); in age_attach()
362 v = CSR_READ_4(sc, AGE_MDIO); in age_miibus_readreg()
396 v = CSR_READ_4(sc, AGE_MDIO); in age_miibus_writereg()
444 reg = CSR_READ_4(sc, AGE_MAC_CFG); in age_miibus_statchg()
446 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | in age_miibus_statchg()
496 status = CSR_READ_4(sc, AGE_INTR_STATUS); in age_intr()
567 reg = CSR_READ_4(sc, AGE_SPI_CTRL); in age_get_macaddr()
580 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | in age_get_macaddr()
[all …]
H A Dif_bgevar.h103 #define CSR_READ_4(sc, reg) \ macro
109 CSR_READ_4(sc, reg); \
113 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))
117 CSR_READ_4(sc, reg); \
120 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))
124 CSR_READ_4(sc, reg); \
H A Dif_stge.c230 #define CSR_READ_4(_sc, reg) \ macro
567 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia) in stge_attach()
805 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0) in stge_dma_wait()
1150 txstat = CSR_READ_4(sc, STGE_TxStatus); in stge_intr()
1443 (void) CSR_READ_4(sc, STGE_OctetRcvOk); in stge_stats_update()
1445 (void) CSR_READ_4(sc, STGE_FramesRcvdOk); in stge_stats_update()
1452 (void) CSR_READ_4(sc, STGE_OctetXmtdOk); in stge_stats_update()
1455 CSR_READ_4(sc, STGE_FramesXmtdOk)); in stge_stats_update()
1458 CSR_READ_4(sc, STGE_LateCollisions) + in stge_stats_update()
1459 CSR_READ_4(sc, STGE_MultiColFrames) + in stge_stats_update()
[all …]
H A Dif_ipw.c146 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); in MEM_READ_4()
1118 r = CSR_READ_4(sc, IPW_CSR_RX_READ); in ipw_rx_intr()
1227 r = CSR_READ_4(sc, IPW_CSR_TX_READ); in ipw_tx_intr()
1255 r = CSR_READ_4(sc, IPW_CSR_INTR); in ipw_intr()
1273 r = CSR_READ_4(sc, IPW_CSR_INTR); in ipw_softintr()
1595 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); in ipw_get_table1()
1600 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA); in ipw_get_table1()
1619 else if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) in ipw_get_radio()
1747 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) in ipw_stop_master()
1754 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | in ipw_stop_master()
[all …]
H A Dif_ti.c244 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; in ti_eeprom_putbyte()
268 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); in ti_eeprom_getbyte()
277 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); in ti_eeprom_getbyte()
285 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); in ti_eeprom_getbyte()
296 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); in ti_eeprom_getbyte()
307 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) in ti_eeprom_getbyte()
1155 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); in ti_setmulti()
1225 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { in ti_64bitslot_war()
1229 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { in ti_64bitslot_war()
1267 if (CSR_READ_4(s in ti_chipinit()
[all...]
H A Dif_iwi.c161 return CSR_READ_4(sc, IWI_CSR_INDIRECT_DATA); in MEM_READ_4()
887 rate = iwi_cvtrate(CSR_READ_4(sc, IWI_CSR_CURRENT_TX_RATE)); in iwi_media_status()
1370 (void)CSR_READ_4(sc, IWI_CSR_CMD_RIDX); in iwi_cmd_intr()
1393 hw = CSR_READ_4(sc, IWI_CSR_RX_RIDX); in iwi_rx_intr()
1442 hw = CSR_READ_4(sc, txq->csr_ridx); in iwi_tx_intr()
1481 if ((r = CSR_READ_4(sc, IWI_CSR_INTR)) == 0 || r == 0xffffffff) in iwi_intr()
1498 if ((r = CSR_READ_4(sc, IWI_CSR_INTR)) == 0 || r == 0xffffffff) in iwi_softintr()
1868 size = uimin(CSR_READ_4(sc, IWI_CSR_TABLE0_SIZE), 128 - 1); in iwi_get_table0()
1958 if (CSR_READ_4(sc, IWI_CSR_RST) & IWI_RST_MASTER_DISABLED) in iwi_stop_master()
1965 CSR_WRITE_4(sc, IWI_CSR_RST, CSR_READ_4(sc, IWI_CSR_RST) | in iwi_stop_master()
[all …]
H A Dif_et.c380 data = CSR_READ_4(sc, ET_MII_IND); in et_miibus_readreg()
394 data = CSR_READ_4(sc, ET_MII_STAT); in et_miibus_readreg()
426 data = CSR_READ_4(sc, ET_MII_IND); in et_miibus_writereg()
474 ctrl = CSR_READ_4(sc, ET_MAC_CTRL); in et_miibus_statchg()
476 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); in et_miibus_statchg()
479 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); in et_miibus_statchg()
523 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); in et_miibus_statchg()
1023 intrs = CSR_READ_4(sc, ET_INTR_STATUS); in et_intr()
1211 if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) { in et_stop_rxdma()
1286 pktfilt = CSR_READ_4(sc, ET_PKTFILT); in et_setmulti()
[all …]
H A Dif_tireg.h966 #define CSR_READ_4(sc, reg) \ macro
972 #define CSR_READ_4(sc, reg) \ macro
977 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))
979 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))
/netbsd-src/sys/arch/arm/xscale/
H A Dixp425_pci_space.c51 #define CSR_READ_4(x) *(volatile uint32_t *) \ macro
272 data = CSR_READ_4(PCI_NP_RDATA); in _pci_io_bs_r_1()
273 if (CSR_READ_4(PCI_ISR) & ISR_PFE) in _pci_io_bs_r_1()
292 data = CSR_READ_4(PCI_NP_RDATA); in _pci_io_bs_r_2()
293 if (CSR_READ_4(PCI_ISR) & ISR_PFE) in _pci_io_bs_r_2()
309 data = CSR_READ_4(PCI_NP_RDATA); in _pci_io_bs_r_4()
310 if (CSR_READ_4(PCI_ISR) & ISR_PFE) in _pci_io_bs_r_4()
332 if (CSR_READ_4(PCI_ISR) & ISR_PFE) in _pci_io_bs_w_1()
352 if (CSR_READ_4(PCI_ISR) & ISR_PFE) in _pci_io_bs_w_2()
367 if (CSR_READ_4(PCI_ISR) & ISR_PFE) in _pci_io_bs_w_4()
H A Dpxa2x0_mci.c149 #define CSR_READ_4(sc, reg) \ macro
154 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (val))
156 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(val))
732 if (ISSET(CSR_READ_4(sc, MMC_STAT), STAT_CLK_EN)) { in pxamci_stop_clock()
735 while (ISSET(CSR_READ_4(sc, MMC_STAT), STAT_CLK_EN) in pxamci_stop_clock()
757 status = CSR_READ_4(sc, MMC_I_REG) & ~CSR_READ_4(sc, MMC_I_MASK); in pxamci_intr()
884 uint32_t h = CSR_READ_4(sc, MMC_RES) & 0xffff; in pxamci_intr_cmd()
885 uint32_t l = CSR_READ_4(sc, MMC_RES) & 0xffff; in pxamci_intr_cmd()
907 uint32_t h = CSR_READ_4(sc, MMC_RES) & 0xffff; in pxamci_intr_cmd()
908 uint32_t m = CSR_READ_4(sc, MMC_RES) & 0xffff; in pxamci_intr_cmd()
[all …]
H A Dpxa2x0_i2c.c407 #define CSR_READ_4(sc,r) bus_space_read_4(sc->sc_iot, sc->sc_ioh, r) macro
423 while (CSR_READ_4(sc, I2C_ICR) & ~ICR_UR) in pxa2x0_i2c_reset()
436 isr = CSR_READ_4(sc, I2C_ISR); in pxa2x0_i2c_wait()
512 *bytep = CSR_READ_4(sc, I2C_IDBR); in pxa2x0_i2c_read_byte()
/netbsd-src/sys/dev/ic/
H A Dbwi.c734 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS); in bwi_softintr()
742 intr_mask = CSR_READ_4(sc, BWI_MAC_INTR_MASK); in bwi_softintr()
766 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask; in bwi_softintr()
809 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) in bwi_softintr()
1242 return (CSR_READ_4(sc, BWI_MOBJ_DATA)); in bwi_mac_lateattach()
1290 CSR_READ_4(mac->mac_sc, BWI_STATE_HI); /* dummy read */ in bwi_mac_init()
1516 state_lo = CSR_READ_4(sc, BWI_STATE_LO); in bwi_mac_test()
1522 CSR_READ_4(sc, BWI_STATE_LO); in bwi_mac_test()
1528 CSR_READ_4(sc, BWI_STATE_LO); in bwi_mac_test()
1533 status = CSR_READ_4(s in bwi_mac_test()
[all...]
H A Dbwivar.h80 #define CSR_READ_4(sc, reg) \ macro
95 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits))
100 CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits))
105 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits))
H A Dwivar.h240 #define CSR_READ_4(sc, reg) \ macro
262 #define CSR_READ_4(sc, reg) \ macro
H A Drtl81x9var.h285 #define CSR_READ_4(sc, reg) \
284 #define CSR_READ_4( global() macro
/netbsd-src/sys/arch/sandpoint/stand/altboot/
H A Dpcn.c47 #define CSR_READ_4(l, r) in32rb((l)->csr+(r)) macro
157 (void)CSR_READ_4(l, PCN_32RESET); in pcn_init()
314 return CSR_READ_4(l, PCN_RDP); in pcn_csr_read()
328 return CSR_READ_4(l, PCN_BDP); in pcn_bcr_read()
H A Dsiisata.c41 #define CSR_READ_4(r) in32rb(r) macro
184 val = CSR_READ_4(ss); /* has completed */ in satapresense()
H A Drge.c52 #define CSR_READ_4(l, r) in32rb((l)->csr+(r)) macro
323 v = CSR_READ_4(l, RGE_PHYAR); in mii_read()
338 v = CSR_READ_4(l, RGE_PHYAR); in mii_write()
H A Dstg.c46 #define CSR_READ_4(l, r) in32rb((l)->csr+(r)) macro
363 reg = CSR_READ_4(l, STGE_AsicCtrl); in stg_reset()
370 if ((CSR_READ_4(l, STGE_AsicCtrl) & AC_ResetBusy) == 0) in stg_reset()
H A Dfxp.c94 #define CSR_READ_4(l, r) in32rb((l)->iobase+(r)) macro
520 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & in fxp_mdi_read()
H A Dskg.c51 #define CSR_READ_4(l, r) in32rb((l)->csr+(r)) macro
463 val = CSR_READ_4(l, SK_GPIO); in mii_initphy()
/netbsd-src/sys/arch/evbarm/ixm1200/
H A Dnappi_nppb.c62 #define CSR_READ_4(sc, reg) \ macro

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