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Searched refs:CP_ME_CNTL (Results 1 – 14 of 14) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_ni.c1471 WREG32(CP_ME_CNTL, 0); in cayman_cp_enable()
1475 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); in cayman_cp_enable()
1853 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); in cayman_gpu_soft_reset()
H A Drv770d.h337 #define CP_ME_CNTL 0x86D8 macro
H A Dnid.h320 #define CP_ME_CNTL 0x86D8 macro
H A Dsid.h1029 #define CP_ME_CNTL 0x86D8 macro
H A Dcikd.h1110 #define CP_ME_CNTL 0x86D8 macro
H A Dradeon_si.c3474 WREG32(CP_ME_CNTL, 0); in si_cp_enable()
3478 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); in si_cp_enable()
3887 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in si_gpu_soft_reset()
4056 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in si_gpu_pci_config_reset()
H A Dradeon_evergreen.c3023 WREG32(CP_ME_CNTL, cp_me); in evergreen_cp_start()
3914 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); in evergreen_gpu_soft_reset()
4024 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); in evergreen_gpu_pci_config_reset()
H A Dradeon_rv770.c1092 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); in r700_cp_stop()
H A Devergreend.h463 #define CP_ME_CNTL 0x86D8 macro
H A Dradeon_cik.c3893 WREG32(CP_ME_CNTL, 0); in cik_cp_gfx_enable()
3897 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); in cik_cp_gfx_enable()
4974 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in cik_gpu_soft_reset()
5178 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in cik_gpu_pci_config_reset()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_gfx_v8_0.c4126 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0); in gfx_v8_0_cp_gfx_enable()
4127 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0); in gfx_v8_0_cp_gfx_enable()
4128 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0); in gfx_v8_0_cp_gfx_enable()
4130 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1); in gfx_v8_0_cp_gfx_enable()
4131 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1); in gfx_v8_0_cp_gfx_enable()
4132 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1); in gfx_v8_0_cp_gfx_enable()
H A Dsid.h1028 #define CP_ME_CNTL 0x21B6 macro
H A Damdgpu_gfx_v10_0.c2398 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); in gfx_v10_0_cp_gfx_enable()
2399 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); in gfx_v10_0_cp_gfx_enable()
2400 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); in gfx_v10_0_cp_gfx_enable()
H A Damdgpu_gfx_v9_0.c3046 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3047 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3048 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()