| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrArithmetic.td | 924 multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
933 def NAME#8rr : BinOpRR_RF<BaseOpc, mnemonic, Xi8 , opnodeflag>;
934 def NAME#16rr : BinOpRR_RF<BaseOpc, mnemonic, Xi16, opnodeflag>;
935 def NAME#32rr : BinOpRR_RF<BaseOpc, mnemonic, Xi32, opnodeflag>;
936 def NAME#64rr : BinOpRR_RF<BaseOpc, mnemonic, Xi64, opnodeflag>;
966 def NAME#8mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi8 , opnode>;
967 def NAME#16mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi16, opnode>;
968 def NAME#32mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi32, opnode>;
969 def NAME#64mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi64, opnode>;
1012 multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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| H A D | X86FastISel.cpp | 2880 unsigned BaseOpc, CondCode; in fastLowerIntrinsicCall() local
2884 BaseOpc = ISD::ADD; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2886 BaseOpc = ISD::ADD; CondCode = X86::COND_B; break; in fastLowerIntrinsicCall()
2888 BaseOpc = ISD::SUB; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2890 BaseOpc = ISD::SUB; CondCode = X86::COND_B; break; in fastLowerIntrinsicCall()
2892 BaseOpc = X86ISD::SMUL; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2894 BaseOpc = X86ISD::UMUL; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2909 if (CI->isOne() && (BaseOpc == ISD::ADD || BaseOpc == ISD::SUB) && in fastLowerIntrinsicCall()
2913 bool IsDec = BaseOpc == ISD::SUB; in fastLowerIntrinsicCall()
2918 ResultReg = fastEmit_ri(VT, VT, BaseOpc, LHSReg, CI->getZExtValue()); in fastLowerIntrinsicCall()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.h | 370 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
388 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
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| H A D | AMDGPUBaseInfo.cpp | 234 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements) { in getMTBUFOpcode() argument
235 const MTBUFInfo *Info = getMTBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements); in getMTBUFOpcode()
264 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements) { in getMUBUFOpcode() argument
265 const MUBUFInfo *Info = getMUBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements); in getMUBUFOpcode()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 701 int BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2ADDspImm in CreateLoadStoreMulti() local
713 BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2SUBspImm in CreateLoadStoreMulti()
736 (BaseOpc == ARM::tADDi8 || BaseOpc == ARM::tSUBi8)) { in CreateLoadStoreMulti()
754 if (BaseOpc == ARM::tADDrSPi) { in CreateLoadStoreMulti()
756 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) in CreateLoadStoreMulti()
761 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) in CreateLoadStoreMulti()
767 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) in CreateLoadStoreMulti()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 881 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(N->getOpcode()); in ScalarizeVecOp_VECREDUCE_SEQ() local
884 return DAG.getNode(BaseOpc, SDLoc(N), N->getValueType(0), in ScalarizeVecOp_VECREDUCE_SEQ()
5072 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(Opc); in WidenVecOp_VECREDUCE() local
5073 SDValue NeutralElem = DAG.getNeutralElement(BaseOpc, dl, ElemVT, Flags); in WidenVecOp_VECREDUCE()
5098 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(Opc); in WidenVecOp_VECREDUCE_SEQ() local
5099 SDValue NeutralElem = DAG.getNeutralElement(BaseOpc, dl, ElemVT, Flags); in WidenVecOp_VECREDUCE_SEQ()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 2995 unsigned BaseOpc = BO.first.getOpcode(); in LowerUnalignedLoad() local
2996 if (BaseOpc == HexagonISD::VALIGNADDR && BO.second % LoadLen == 0) in LowerUnalignedLoad()
3004 SDValue BaseNoOff = (BaseOpc != HexagonISD::VALIGNADDR) in LowerUnalignedLoad()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 3563 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(Op.getOpcode()); in lowerVECREDUCE() local
3572 Vec = DAG.getNode(BaseOpc, DL, VecEVT, Lo, Hi); in lowerVECREDUCE()
3598 DAG.getNeutralElement(BaseOpc, DL, VecEltVT, SDNodeFlags()); in lowerVECREDUCE()
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