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Searched refs:BaseOffs (Results 1 – 19 of 19) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp2469 if (BaseOffs != other.BaseOffs) in compare()
2491 return !BaseOffs && !Scale && !(BaseGV && BaseReg); in isTrivial()
2505 return ConstantInt::get(IntPtrTy, BaseOffs); in GetFieldAsValue()
2542 BaseOffs = 0; in SetCombinedField()
2570 if (BaseOffs) { in print()
2572 << BaseOffs; in print()
3885 TestAddrMode.BaseOffs += CI->getSExtValue() * TestAddrMode.Scale; in matchScaledValue()
3933 if (AddrMode.BaseOffs) { in matchScaledValue()
3946 TestAddrMode.BaseOffs -= Offset.getLimitedValue(); in matchScaledValue()
4602 AddrMode.BaseOffs += ConstantOffset; in matchOperationAddr()
[all …]
H A DTargetLoweringBase.cpp1899 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) in isLegalAddressingMode()
1911 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
1916 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1887 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs); in isLegalAddressingMode()
1892 AM.BaseOffs%4 == 0; in isLegalAddressingMode()
1899 return isImmUs(AM.BaseOffs); in isLegalAddressingMode()
1902 return AM.Scale == 1 && AM.BaseOffs == 0; in isLegalAddressingMode()
1907 return isImmUs2(AM.BaseOffs); in isLegalAddressingMode()
1910 return AM.Scale == 2 && AM.BaseOffs == 0; in isLegalAddressingMode()
1914 return isImmUs4(AM.BaseOffs); in isLegalAddressingMode()
1917 return AM.Scale == 4 && AM.BaseOffs == 0; in isLegalAddressingMode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUPerfHintAnalysis.cpp239 auto *Ptr = GetPointerBaseWithConstantOffset(GEP, AM.BaseOffs, *DL); in visit()
H A DSIISelLowering.cpp1236 return AM.BaseOffs == 0 && AM.Scale == 0; in isLegalFlatAddressingMode()
1240 (AM.BaseOffs == 0 || in isLegalFlatAddressingMode()
1242 AM.BaseOffs, AMDGPUAS::FLAT_ADDRESS, SIInstrFlags::FLAT)); in isLegalFlatAddressingMode()
1248 (AM.BaseOffs == 0 || Subtarget->getInstrInfo()->isLegalFLATOffset( in isLegalGlobalAddressingMode()
1249 AM.BaseOffs, AMDGPUAS::GLOBAL_ADDRESS, in isLegalGlobalAddressingMode()
1278 if (!SIInstrInfo::isLegalMUBUFImmOffset(AM.BaseOffs)) in isLegalMUBUFAddressingMode()
1319 if (AM.BaseOffs % 4 != 0) in isLegalAddressingMode()
1331 if (!isUInt<8>(AM.BaseOffs / 4)) in isLegalAddressingMode()
1336 if (!isUInt<32>(AM.BaseOffs / 4)) in isLegalAddressingMode()
1340 if (!isUInt<20>(AM.BaseOffs)) in isLegalAddressingMode()
[all …]
H A DSILoadStoreOptimizer.cpp1929 AM.BaseOffs = Dist; in promoteConstantOffsetToImm()
1954 AM.BaseOffs = P.second - AnchorAddr.Offset; in promoteConstantOffsetToImm()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h303 AM.BaseOffs = BaseOffset;
338 AM.BaseOffs = BaseOffset; in getScalingFactorCost()
H A DTargetLowering.h2331 int64_t BaseOffs = 0; member
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp3384 if (!isAligned(A, AM.BaseOffs)) in isLegalAddressingMode()
3387 if (!isInt<11>(AM.BaseOffs >> Log2(A))) in isLegalAddressingMode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp850 int64_t Offs = AM.BaseOffs; in isLegalAddressingMode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp647 if (AM.BaseOffs < 0) in isLegalAddressingMode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp15815 if (Ty->isVectorTy() && AM.BaseOffs != 0 && !Subtarget.hasP9Vector()) in isLegalAddressingMode()
15819 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) in isLegalAddressingMode()
15831 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
15836 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp4209 return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale; in isLegalAddressingMode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp970 if (!isInt<20>(AM.BaseOffs)) in isLegalAddressingMode()
977 if (!SupportedAM.LongDisplacement && !isUInt<12>(AM.BaseOffs)) in isLegalAddressingMode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1037 AM.BaseOffs = C2APIntVal.getSExtValue(); in reassociationCanBreakAddressingModePattern()
1045 AM.BaseOffs = CombinedValue; in reassociationCanBreakAddressingModePattern()
2079 AM.BaseOffs = Offset->getSExtValue(); in canFoldInAddressingMode()
2088 AM.BaseOffs = -Offset->getSExtValue(); in canFoldInAddressingMode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp11718 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale) in isLegalAddressingMode()
11723 return AM.HasBaseReg && !AM.BaseOffs && !AM.Scale; in isLegalAddressingMode()
11736 int64_t Offset = AM.BaseOffs; in isLegalAddressingMode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp871 if (!isInt<12>(AM.BaseOffs)) in isLegalAddressingMode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp17704 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) in isLegalAddressingMode()
17716 if (AM.BaseOffs) in isLegalAddressingMode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp31678 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr)) in isLegalAddressingMode()
31695 Subtarget.is64Bit() && (AM.BaseOffs || AM.Scale > 1)) in isLegalAddressingMode()