| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.cpp | 36 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignArgRegs() local
40 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs()
42 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs()
49 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs()
61 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128() local
65 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
67 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
74 State.AllocateReg(ArgRegs[RegNum + i]); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
86 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignFPArgRegs() local
91 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
[all …]
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| H A D | PPCFastISel.cpp | 185 SmallVectorImpl<unsigned> &ArgRegs,
1373 SmallVectorImpl<unsigned> &ArgRegs, in processCallArgs() argument
1430 unsigned Arg = ArgRegs[VA.getValNo()]; in processCallArgs()
1601 SmallVector<unsigned, 8> ArgRegs; in fastLowerCall() local
1606 ArgRegs.reserve(NumArgs); in fastLowerCall()
1635 ArgRegs.push_back(Arg); in fastLowerCall()
1644 if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, in fastLowerCall()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsCallLowering.cpp | 466 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); in lowerFormalArguments() local
467 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); in lowerFormalArguments()
471 if (ArgRegs.size() == Idx) in lowerFormalArguments()
476 (int)(RegSize * (ArgRegs.size() - Idx)); in lowerFormalArguments()
483 for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += RegSize) { in lowerFormalArguments()
484 MIRBuilder.getMBB().addLiveIn(ArgRegs[I]); in lowerFormalArguments()
487 MIRBuilder.buildCopy(LLT::scalar(RegSize * 8), Register(ArgRegs[I])); in lowerFormalArguments()
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| H A D | MipsISelLowering.cpp | 4385 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); in passByValArg() local
4396 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4445 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4468 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); in writeVarArgRegs() local
4469 unsigned Idx = State.getFirstUnallocated(ArgRegs); in writeVarArgRegs()
4480 if (ArgRegs.size() == Idx) in writeVarArgRegs()
4485 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); in writeVarArgRegs()
4497 for (unsigned I = Idx; I < ArgRegs.size(); in writeVarArgRegs()
4499 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); in writeVarArgRegs()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 520 static const MCPhysReg ArgRegs[] = {ARC::R0, ARC::R1, ARC::R2, ARC::R3, in LowerCallArguments() local
523 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs); in LowerCallArguments()
524 if (FirstVAReg < array_lengthof(ArgRegs)) { in LowerCallArguments()
531 MFI.CreateFixedObject((array_lengthof(ArgRegs) - FirstVAReg) * 4, in LowerCallArguments()
535 for (unsigned i = FirstVAReg; i < array_lengthof(ArgRegs); i++) { in LowerCallArguments()
538 RegInfo.addLiveIn(ArgRegs[i], VReg); in LowerCallArguments()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.h | 56 SmallVectorImpl<std::pair<MCRegister, Register>> &ArgRegs,
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| H A D | AMDGPUCallLowering.cpp | 751 … SmallVectorImpl<std::pair<MCRegister, Register>> &ArgRegs, in passSpecialInputs() argument
807 ArgRegs.emplace_back(OutgoingArg->getRegister(), InputReg); in passSpecialInputs()
885 ArgRegs.emplace_back(OutgoingArg->getRegister(), InputReg); in passSpecialInputs()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 218 SmallVectorImpl<Register> &ArgRegs,
1872 SmallVectorImpl<Register> &ArgRegs, in ProcessCallArgs() argument
1939 Register Arg = ArgRegs[VA.getValNo()]; in ProcessCallArgs()
2219 SmallVector<Register, 8> ArgRegs; in ARMEmitLibcall() local
2223 ArgRegs.reserve(I->getNumOperands()); in ARMEmitLibcall()
2238 ArgRegs.push_back(Arg); in ARMEmitLibcall()
2246 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, in ARMEmitLibcall()
2328 SmallVector<Register, 8> ArgRegs; in SelectCall() local
2333 ArgRegs.reserve(arg_size); in SelectCall()
2371 ArgRegs.push_back(Arg); in SelectCall()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CallLowering.h | 568 ArrayRef<ArrayRef<Register>> ArgRegs, Register SwiftErrorVReg,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 1345 static const MCPhysReg ArgRegs[] = { in LowerCCCArguments() local
1349 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs); in LowerCCCArguments()
1350 if (FirstVAReg < array_lengthof(ArgRegs)) { in LowerCCCArguments()
1354 for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) { in LowerCCCArguments()
1364 RegInfo.addLiveIn(ArgRegs[i], VReg); in LowerCCCArguments()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CallLowering.cpp | 82 ArrayRef<ArrayRef<Register>> ArgRegs, in lowerCall() argument
117 ArgInfo OrigArg{ArgRegs[i], *Arg.get(), getAttributesForArgIdx(CB, i), in lowerCall()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 140 static const MCPhysReg ArgRegs[] = { in CC_SkipOdd() local
144 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_SkipOdd()
145 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_SkipOdd()
149 State.AllocateReg(ArgRegs[RegNum]); in CC_SkipOdd()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 534 static const MCPhysReg ArgRegs[] = { in LowerFormalArguments_32() local
537 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs); in LowerFormalArguments_32()
538 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6; in LowerFormalArguments_32()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 3235 SmallVector<unsigned, 16> ArgRegs; in fastLowerCall() local
3279 ArgRegs.push_back(ResultReg); in fastLowerCall()
3311 unsigned ArgReg = ArgRegs[VA.getValNo()]; in fastLowerCall()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 7296 ArrayRef<MCPhysReg> ArgRegs = makeArrayRef(ArgGPRs); in LowerFormalArguments() local
7297 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); in LowerFormalArguments()
7310 if (ArgRegs.size() == Idx) { in LowerFormalArguments()
7314 VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx); in LowerFormalArguments()
7333 for (unsigned I = Idx; I < ArgRegs.size(); in LowerFormalArguments()
7336 RegInfo.addLiveIn(ArgRegs[I], Reg); in LowerFormalArguments()
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