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Searched refs:ARM (Results 1 – 25 of 1477) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp185 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
186 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
187 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
188 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
189 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
190 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
192 { ARM::VLD1d16QPseudo, ARM::VLD1d16Q, true, false, false, SingleSpc, 4, 4 ,false},
193 { ARM::VLD1d16TPseudo, ARM::VLD1d16T, true, false, false, SingleSpc, 3, 4 ,false},
194 { ARM::VLD1d32QPseudo, ARM::VLD1d32Q, true, false, false, SingleSpc, 4, 2 ,false},
195 { ARM::VLD1d32TPseudo, ARM::VLD1d32T, true, false, false, SingleSpc, 3, 2 ,false},
[all …]
H A DARMFeatures.h28 case ARM::tADC: in isV8EligibleForIT()
29 case ARM::tADDi3: in isV8EligibleForIT()
30 case ARM::tADDi8: in isV8EligibleForIT()
31 case ARM::tADDrr: in isV8EligibleForIT()
32 case ARM::tAND: in isV8EligibleForIT()
33 case ARM::tASRri: in isV8EligibleForIT()
34 case ARM::tASRrr: in isV8EligibleForIT()
35 case ARM::tBIC: in isV8EligibleForIT()
36 case ARM::tEOR: in isV8EligibleForIT()
37 case ARM::tLSLri: in isV8EligibleForIT()
[all …]
H A DARMBaseInstrInfo.cpp93 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
94 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
95 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
96 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
97 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
98 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
99 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
100 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
103 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
104 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
[all …]
H A DARMRegisterBankInfo.cpp30 namespace ARM { namespace
142 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID); in ARMRegisterBankInfo()
144 assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up"); in ARMRegisterBankInfo()
147 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && in ARMRegisterBankInfo()
149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && in ARMRegisterBankInfo()
151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && in ARMRegisterBankInfo()
153 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && in ARMRegisterBankInfo()
155 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && in ARMRegisterBankInfo()
157 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && in ARMRegisterBankInfo()
159 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnoip_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
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H A DThumb2SizeReduction.cpp83 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0,0 },
84 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
85 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
86 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1,0 },
87 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
88 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0,0 },
89 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
90 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
91 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0,0 },
94 { ARM::t2CMNzrr, ARM::tCMNz, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
[all …]
H A DThumb2InstrInfo.cpp53 return MCInstBuilder(ARM::tHINT).addImm(0).addImm(ARMCC::AL).addReg(0); in getNop()
92 if (MBBI->getOpcode() == ARM::t2IT) { in ReplaceTailWithBranchTo()
140 get(ARM::t2CSEL), DestReg) in optimizeSelect()
155 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
158 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
177 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
178 BuildMI(MBB, I, DL, get(ARM::t2STRi12)) in storeRegToStackSlot()
187 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
193 MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass); in storeRegToStackSlot()
196 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8)); in storeRegToStackSlot()
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H A DARMLoadStoreOptimizer.cpp209 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead()) in definesCPSR()
220 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD; in getMemoryOpOffset()
224 if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 || in getMemoryOpOffset()
225 Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 || in getMemoryOpOffset()
226 Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 || in getMemoryOpOffset()
227 Opcode == ARM::LDRi12 || Opcode == ARM::STRi12) in getMemoryOpOffset()
231 if (Opcode == ARM::tLDRi || Opcode == ARM::tSTRi || in getMemoryOpOffset()
232 Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) in getMemoryOpOffset()
257 case ARM::LDRi12: in getLoadStoreMultipleOpcode()
261 case ARM_AM::ia: return ARM::LDMIA; in getLoadStoreMultipleOpcode()
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H A DARMBaseInstrInfo.h368 return MI->getOpcode() == ARM::t2LoopEndDec || in isUnspillableTerminatorImpl()
369 MI->getOpcode() == ARM::t2DoLoopStartTP || in isUnspillableTerminatorImpl()
370 MI->getOpcode() == ARM::t2WhileLoopStartLR; in isUnspillableTerminatorImpl()
556 return MachineOperand::CreateReg(ARM::CPSR,
563 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; in isUncondBranchOpcode()
570 return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 || in isVPTOpcode()
571 Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 || in isVPTOpcode()
572 Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 || in isVPTOpcode()
573 Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 || in isVPTOpcode()
574 Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 || in isVPTOpcode()
[all …]
H A DARMInstrInfo.cpp38 NopInst.setOpcode(ARM::HINT); in getNop()
43 NopInst.setOpcode(ARM::MOVr); in getNop()
44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop()
45 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop()
57 case ARM::LDR_PRE_IMM: in getUnindexedOpcode()
58 case ARM::LDR_PRE_REG: in getUnindexedOpcode()
59 case ARM::LDR_POST_IMM: in getUnindexedOpcode()
60 case ARM::LDR_POST_REG: in getUnindexedOpcode()
61 return ARM::LDRi12; in getUnindexedOpcode()
62 case ARM::LDRH_PRE: in getUnindexedOpcode()
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H A DThumb1FrameLowering.cpp79 if (ScratchReg == ARM::NoRegister) in emitPrologueEpilogueSPUpdate()
84 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ScratchReg) in emitPrologueEpilogueSPUpdate()
90 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDhirr), ARM::SP) in emitPrologueEpilogueSPUpdate()
91 .addReg(ARM::SP) in emitPrologueEpilogueSPUpdate()
99 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, in emitPrologueEpilogueSPUpdate()
109 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, in emitCallSPUpdate()
136 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { in eliminateCallFramePseudoInstr()
139 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); in eliminateCallFramePseudoInstr()
184 ARM::NoRegister, MachineInstr::FrameSetup); in emitPrologue()
197 ARM::NoRegister, MachineInstr::FrameSetup); in emitPrologue()
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H A DARMTargetTransformInfo.h72 ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON, ARM::FeatureThumb2,
73 ARM::FeatureFP16, ARM::FeatureVFP4, ARM::FeatureFPARMv8,
74 ARM::FeatureFullFP16, ARM::FeatureFP16FML, ARM::FeatureHWDivThumb,
75 ARM::FeatureHWDivARM, ARM::FeatureDB, ARM::FeatureV7Clrex,
76 ARM::FeatureAcquireRelease, ARM::FeatureSlowFPBrcc,
77 ARM::FeaturePerfMon, ARM::FeatureTrustZone, ARM::Feature8MSecExt,
78 ARM::FeatureCrypto, ARM::FeatureCRC, ARM::FeatureRAS,
79 ARM::FeatureFPAO, ARM::FeatureFuseAES, ARM::FeatureZCZeroing,
80 ARM::FeatureProfUnpredicate, ARM::FeatureSlowVGETLNi32,
81 ARM::FeatureSlowVDUP32, ARM::FeaturePreferVMOVSR,
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H A DARMAsmPrinter.cpp184 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX) in runOnMachineFunction()
219 if(ARM::GPRPairRegClass.contains(Reg)) { in printOperand()
222 Reg = TRI->getSubReg(Reg, ARM::gsub_0); in printOperand()
293 if (!ARM::DPRRegClass.contains(*SR)) in PrintAsmOperand()
295 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg; in PrintAsmOperand()
320 if (ARM::GPRPairRegClass.contains(RegBegin)) { in PrintAsmOperand()
322 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); in PrintAsmOperand()
324 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1); in PrintAsmOperand()
384 ARM::GPRPairRegClass.hasSubClassEq(TRI->getRegClass(RC))) { in PrintAsmOperand()
392 TRI->getSubReg(MO.getReg(), FirstHalf ? ARM::gsub_0 : ARM::gsub_1); in PrintAsmOperand()
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H A DARMFrameLowering.cpp259 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes, in emitSPUpdate()
266 case ARM::VSTMDDB_UPD: in sizeOfSPAdjustment()
269 case ARM::STMDB_UPD: in sizeOfSPAdjustment()
270 case ARM::t2STMDB_UPD: in sizeOfSPAdjustment()
273 case ARM::t2STR_PRE: in sizeOfSPAdjustment()
274 case ARM::STR_PRE_IMM: in sizeOfSPAdjustment()
377 BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg) in emitAligningInstructions()
382 BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg) in emitAligningInstructions()
392 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) in emitAligningInstructions()
397 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) in emitAligningInstructions()
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H A DMVETailPredUtils.h30 case ARM::MVE_VCTP8: in VCTPOpcodeToLSTP()
31 return IsDoLoop ? ARM::MVE_DLSTP_8 : ARM::MVE_WLSTP_8; in VCTPOpcodeToLSTP()
32 case ARM::MVE_VCTP16: in VCTPOpcodeToLSTP()
33 return IsDoLoop ? ARM::MVE_DLSTP_16 : ARM::MVE_WLSTP_16; in VCTPOpcodeToLSTP()
34 case ARM::MVE_VCTP32: in VCTPOpcodeToLSTP()
35 return IsDoLoop ? ARM::MVE_DLSTP_32 : ARM::MVE_WLSTP_32; in VCTPOpcodeToLSTP()
36 case ARM::MVE_VCTP64: in VCTPOpcodeToLSTP()
37 return IsDoLoop ? ARM::MVE_DLSTP_64 : ARM::MVE_WLSTP_64; in VCTPOpcodeToLSTP()
46 case ARM::MVE_VCTP8: in getTailPredVectorWidth()
48 case ARM::MVE_VCTP16: in getTailPredVectorWidth()
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H A DARMISelDAGToDAG.cpp112 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32); in SelectCMOVPred()
505 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasNoVMLxHazardUse()
1587 Opcode = ARM::LDR_PRE_IMM; in tryARMIndexedLoad()
1591 Opcode = ARM::LDR_POST_IMM; in tryARMIndexedLoad()
1595 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG; in tryARMIndexedLoad()
1602 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST) in tryARMIndexedLoad()
1603 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST); in tryARMIndexedLoad()
1608 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST; in tryARMIndexedLoad()
1614 Opcode = ARM::LDRB_PRE_IMM; in tryARMIndexedLoad()
1618 Opcode = ARM::LDRB_POST_IMM; in tryARMIndexedLoad()
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H A DARMCallingConv.cpp24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS()
65 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64AssignAAPCS()
66 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64AssignAAPCS()
67 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 }; in f64AssignAAPCS()
68 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS()
75 assert((!Reg || Reg == ARM::R3) && "Wrong GPRs usage for f64"); in f64AssignAAPCS()
116 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64RetAssign()
117 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64RetAssign()
153 static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
155 static const MCPhysReg SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
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H A DARMSLSHardening.cpp86 ProduceSB ? (ST->isThumb() ? ARM::t2SpeculationBarrierSBEndBB in insertSpeculationBarrier()
87 : ARM::SpeculationBarrierSBEndBB) in insertSpeculationBarrier()
88 : (ST->isThumb() ? ARM::t2SpeculationBarrierISBDSBEndBB in insertSpeculationBarrier()
89 : ARM::SpeculationBarrierISBDSBEndBB); in insertSpeculationBarrier()
134 {"__llvm_slsblr_thunk_arm_r0", ARM::R0, false},
135 {"__llvm_slsblr_thunk_arm_r1", ARM::R1, false},
136 {"__llvm_slsblr_thunk_arm_r2", ARM::R2, false},
137 {"__llvm_slsblr_thunk_arm_r3", ARM::R3, false},
138 {"__llvm_slsblr_thunk_arm_r4", ARM::R4, false},
139 {"__llvm_slsblr_thunk_arm_r5", ARM::R5, false},
[all …]
H A DThumbRegisterInfo.cpp48 if (ARM::tGPRRegClass.hasSubClassEq(RC)) in getLargestLegalSuperClass()
49 return &ARM::tGPRRegClass; in getLargestLegalSuperClass()
58 return &ARM::tGPRRegClass; in getPointerRegClass()
75 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci)) in emitThumb1LoadConstPool()
94 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci)) in emitThumb2LoadConstPool()
142 if (DestReg == ARM::SP) in emitThumbRegPlusImmInReg()
143 assert(BaseReg == ARM::SP && "Unexpected!"); in emitThumbRegPlusImmInReg()
145 LdReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass); in emitThumbRegPlusImmInReg()
148 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg) in emitThumbRegPlusImmInReg()
153 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg) in emitThumbRegPlusImmInReg()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Support/
H A DARMTargetParser.def1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
9 // This file provides defines to build up the ARM target parser's logic.
49 ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE)
51 FK_NONE, ARM::AEK_NONE)
53 FK_NONE, ARM::AEK_NONE)
55 FK_NONE, ARM::AEK_NONE)
57 FK_NONE, ARM::AEK_NONE)
59 FK_NONE, ARM::AEK_NONE)
61 FK_NONE, ARM::AEK_NONE)
63 FK_NONE, ARM::AEK_NONE)
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMTargetStreamer.cpp110 void ARMTargetStreamer::emitArch(ARM::ArchKind Arch) {} in emitArch()
112 void ARMTargetStreamer::emitObjectArch(ARM::ArchKind Arch) {} in emitObjectArch()
123 if (STI.hasFeature(ARM::HasV8Ops)) { in getArchForCPU()
124 if (STI.hasFeature(ARM::FeatureRClass)) in getArchForCPU()
127 } else if (STI.hasFeature(ARM::HasV8_1MMainlineOps)) in getArchForCPU()
129 else if (STI.hasFeature(ARM::HasV8MMainlineOps)) in getArchForCPU()
131 else if (STI.hasFeature(ARM::HasV7Ops)) { in getArchForCPU()
132 if (STI.hasFeature(ARM::FeatureMClass) && STI.hasFeature(ARM::FeatureDSP)) in getArchForCPU()
135 } else if (STI.hasFeature(ARM::HasV6T2Ops)) in getArchForCPU()
137 else if (STI.hasFeature(ARM::HasV8MBaselineOps)) in getArchForCPU()
[all …]
H A DARMAsmBackend.cpp71 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = { in getFixupKindInfo()
125 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = { in getFixupKindInfo()
209 bool HasThumb2 = STI.getFeatureBits()[ARM::FeatureThumb2]; in getRelaxedOpcode()
210 bool HasV8MBaselineOps = STI.getFeatureBits()[ARM::HasV8MBaselineOps]; in getRelaxedOpcode()
215 case ARM::tBcc: in getRelaxedOpcode()
216 return HasThumb2 ? (unsigned)ARM::t2Bcc : Op; in getRelaxedOpcode()
217 case ARM::tLDRpci: in getRelaxedOpcode()
218 return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op; in getRelaxedOpcode()
219 case ARM::tADR: in getRelaxedOpcode()
220 return HasThumb2 ? (unsigned)ARM::t2ADR : Op; in getRelaxedOpcode()
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H A DARMMCTargetDesc.cpp41 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] && in getMCRDeprecationInfo()
68 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] && in getMCRDeprecationInfo()
80 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] && in getMRCDeprecationInfo()
92 if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() && in getITDeprecationInfo()
104 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] && in getARMStoreDeprecationInfo()
110 if (MI.getOperand(OI).getReg() == ARM::PC) { in getARMStoreDeprecationInfo()
120 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] && in getARMLoadDeprecationInfo()
130 case ARM::LR: in getARMLoadDeprecationInfo()
133 case ARM::PC: in getARMLoadDeprecationInfo()
156 ARM::ArchKind ArchID = ARM::parseArch(TT.getArchName()); in ParseARMTriple()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp587 case ARM::HVC: { in checkDecodedInstruction()
597 case ARM::t2ADDri: in checkDecodedInstruction()
598 case ARM::t2ADDri12: in checkDecodedInstruction()
599 case ARM::t2ADDrr: in checkDecodedInstruction()
600 case ARM::t2ADDrs: in checkDecodedInstruction()
601 case ARM::t2SUBri: in checkDecodedInstruction()
602 case ARM::t2SUBri12: in checkDecodedInstruction()
603 case ARM::t2SUBrr: in checkDecodedInstruction()
604 case ARM::t2SUBrs: in checkDecodedInstruction()
605 if (MI.getOperand(0).getReg() == ARM::SP && in checkDecodedInstruction()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp120 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {} in UnwindContext()
179 FPReg = ARM::SP; in reset()
303 ITInst.setOpcode(ARM::t2IT); in flushPendingInstructions()
360 return MRI->getSubReg(QReg, ARM::dsub_0); in getDRegFromQReg()
510 return getSTI().getFeatureBits()[ARM::ModeThumb]; in isThumb()
514 return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2]; in isThumbOne()
518 return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2]; in isThumbTwo()
522 return getSTI().getFeatureBits()[ARM::HasV4TOps]; in hasThumb()
526 return getSTI().getFeatureBits()[ARM::FeatureThumb2]; in hasThumb2()
530 return getSTI().getFeatureBits()[ARM::HasV6Ops]; in hasV6Ops()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Support/
H A DARMTargetParser.cpp28 ARM::ArchKind ARM::parseArch(StringRef Arch) { in parseArch()
39 unsigned ARM::parseArchVersion(StringRef Arch) { in parseArchVersion()
92 ARM::ProfileKind ARM::parseArchProfile(StringRef Arch) { in parseArchProfile()
140 StringRef ARM::getArchSynonym(StringRef Arch) { in getArchSynonym()
167 bool ARM::getFPUFeatures(unsigned FPUKind, std::vector<StringRef> &Features) { in getFPUFeatures()
232 ARM::EndianKind ARM::parseArchEndian(StringRef Arch) { in parseArchEndian()
251 ARM::ISAKind ARM::parseArchISA(StringRef Arch) { in parseArchISA()
256 .StartsWith("arm", ISAKind::ARM) in parseArchISA()
260 unsigned ARM::parseFPU(StringRef FPU) { in parseFPU()
269 ARM::NeonSupportLevel ARM::getFPUNeonSupportLevel(unsigned FPUKind) { in getFPUNeonSupportLevel()
[all …]

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