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/llvm-project/llvm/test/Analysis/CostModel/RISCV/
H A Dactive_lane_mask.ll6 …2 for instruction: %mask_nxv16i1_i64 = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.…
7 … 16 for instruction: %mask_nxv8i1_i64 = call <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i…
8 …f 8 for instruction: %mask_nxv4i1_i64 = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i…
9 …f 4 for instruction: %mask_nxv2i1_i64 = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i…
10 …f 2 for instruction: %mask_nxv1i1_i64 = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i…
11 …6 for instruction: %mask_nxv16i1_i32 = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.…
12 …f 8 for instruction: %mask_nxv8i1_i32 = call <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i…
13 …f 4 for instruction: %mask_nxv4i1_i32 = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i…
14 …f 2 for instruction: %mask_nxv2i1_i32 = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i…
15 …f 2 for instruction: %mask_nxv1i1_i32 = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i…
[all …]
/llvm-project/llvm/test/Analysis/CostModel/ARM/
H A Dactive_lane_mask.ll6 ; CHECK-NEXT: Cost Model: Found an estimated cost of 176 for instruction: %mask_v16i1_i64 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 undef, i64 undef)
7 ; CHECK-NEXT: Cost Model: Found an estimated cost of 88 for instruction: %mask_v8i1_i64 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 undef, i64 undef)
8 ; CHECK-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %mask_v4i1_i64 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 undef, i64 undef)
9 ; CHECK-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %mask_v2i1_i64 = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64 undef, i64 undef)
10 ; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %mask_v16i1_i32 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 undef, i32 undef)
11 ; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %mask_v8i1_i32 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 undef, i32 undef)
12 ; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %mask_v4i1_i32 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 undef, i32 undef)
13 ; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %mask_v2i1_i32 = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 undef, i32 undef)
14 ; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %mask_v16i1_i16 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i16(i16 undef, i16 undef)
15 ; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %mask_v8i1_i16 = call <8 x i1> @llvm.get.active
[all...]
H A Dmve-active_lane_mask.ll7 ; predicated) should not really be free. We currently assume that all active
12 …del: Found an estimated cost of 0 for instruction: %active.lane.mask = call <4 x i1> @llvm.get.act…
15 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %TC)
21 …del: Found an estimated cost of 0 for instruction: %active.lane.mask = call <8 x i1> @llvm.get.act…
24 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %TC)
30 …el: Found an estimated cost of 0 for instruction: %active.lane.mask = call <16 x i1> @llvm.get.act…
33 %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 %index, i32 %TC)
37 declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
38 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
39 declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32)
/llvm-project/llvm/test/CodeGen/AArch64/
H A Dactive_lane_mask.ll11 %active.lane.mask = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i32(i32 %index, i32 %TC)
12 ret <vscale x 16 x i1> %active.lane.mask
20 %active.lane.mask = call <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i32(i32 %index, i32 %TC)
21 ret <vscale x 8 x i1> %active.lane.mask
29 %active.lane.mask = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 %index, i32 %TC)
30 ret <vscale x 4 x i1> %active.lane.mask
38 %active
[all...]
H A Dcomplex-deinterleaving-reductions-predicated-scalable.ll56 %active.lane.mask.entry = tail call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 0, i64 100)
65 %active.lane.mask = phi <vscale x 2 x i1> [ %active.lane.mask.entry, %entry ], [ %active.lane.mask.next, %vector.body ]
70 %interleaved.mask = tail call <vscale x 4 x i1> @llvm.vector.interleave2.nxv4i1(<vscale x 2 x i1> %active.lane.mask, <vscale x 2 x i1> %active.lane.mask)
75 %interleaved.mask28 = tail call <vscale x 4 x i1> @llvm.vector.interleave2.nxv4i1(<vscale x 2 x i1> %active.lane.mask, <vscale x 2 x i1> %active.lane.mask)
88 %15 = select fast <vscale x 2 x i1> %active
[all...]
/llvm-project/llvm/test/Analysis/Lint/
H A Dget-active-lane-mask.ll6 ; CHECK-NEXT: %res = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %IV, i32 0)
8 %res = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %IV, i32 0)
15 ; CHECK-NOT: call <4 x i1> @llvm.get.active.lane.mask
17 %res = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %IV, i32 1)
24 ; CHECK-NOT: call <4 x i1> @llvm.get.active.lane.mask
26 %res = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %IV, i32 -1)
33 ; CHECK-NOT: call <4 x i1> @llvm.get.active.lane.mask
35 %res = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %IV, i32 %TC)
39 declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
/llvm-project/llvm/test/Transforms/InstSimplify/ConstProp/
H A Dactive-lane-mask.ll12 %int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 0)
22 %int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 1)
32 %int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 8)
42 %int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 15)
52 %int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 16)
62 %int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 100)
72 %int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 -1)
82 %int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 10, i32 11)
92 %int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 12, i32 11)
104 %int = call <8 x i1> @llvm.get.active
[all...]
/llvm-project/llvm/test/CodeGen/Thumb2/LowOverheadLoops/
H A Dtail-pred-basic.ll32 %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 %index, i32 %N)
33 …il call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %tmp, i32 4, <16 x i1> %active.lane.mask, <16 x i…
35 …l call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %tmp3, i32 4, <16 x i1> %active.lane.mask, <16 x i…
38 …tail call void @llvm.masked.store.v16i8.p0(<16 x i8> %mul, ptr %tmp6, i32 4, <16 x i1> %active.lan…
77 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %N)
78 …ail call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %tmp, i32 4, <8 x i1> %active.lane.mask, <8 x i1…
80 …il call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %tmp3, i32 4, <8 x i1> %active.lane.mask, <8 x i1…
83 …tail call void @llvm.masked.store.v8i16.p0(<8 x i16> %mul, ptr %tmp6, i32 4, <8 x i1> %active.lane…
121 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %N)
122 …ail call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %tmp, i32 4, <4 x i1> %active.lane.mask, <4 x i3…
[all …]
H A Dconstbound.ll40 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 500)
43 …%wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %1, i32 4, <4 x i1> %active.lane…
44 %2 = select <4 x i1> %active.lane.mask, <4 x i32> %wide.masked.load, <4 x i32> zeroinitializer
77 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 501)
80 …%wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %1, i32 4, <4 x i1> %active.lane…
81 %2 = select <4 x i1> %active.lane.mask, <4 x i32> %wide.masked.load, <4 x i32> zeroinitializer
114 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 502)
117 …%wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %1, i32 4, <4 x i1> %active.lane…
118 %2 = select <4 x i1> %active.lane.mask, <4 x i32> %wide.masked.load, <4 x i32> zeroinitializer
151 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 503)
[all …]
H A Dtail-pred-intrinsic-round.ll35 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n)
36 …l <4 x float> @llvm.masked.load.v4f32.p0(ptr %next.gep, i32 4, <4 x i1> %active.lane.mask, <4 x fl…
38 …call void @llvm.masked.store.v4f32.p0(<4 x float> %0, ptr %next.gep14, i32 4, <4 x i1> %active.lan…
78 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n)
79 …l <4 x float> @llvm.masked.load.v4f32.p0(ptr %next.gep, i32 4, <4 x i1> %active.lane.mask, <4 x fl…
81 …call void @llvm.masked.store.v4f32.p0(<4 x float> %0, ptr %next.gep14, i32 4, <4 x i1> %active.lan…
121 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n)
122 …l <4 x float> @llvm.masked.load.v4f32.p0(ptr %next.gep, i32 4, <4 x i1> %active.lane.mask, <4 x fl…
124 …call void @llvm.masked.store.v4f32.p0(<4 x float> %0, ptr %next.gep14, i32 4, <4 x i1> %active.lan…
164 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n)
[all …]
H A Dtail-pred-intrinsic-sub-sat.ll37 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %blockSize)
38 …all <8 x i16> @llvm.masked.load.v8i16.p0(ptr %next.gep, i32 2, <8 x i1> %active.lane.mask, <8 x i1…
39 …l <8 x i16> @llvm.masked.load.v8i16.p0(ptr %next.gep21, i32 2, <8 x i1> %active.lane.mask, <8 x i1…
41 …call void @llvm.masked.store.v8i16.p0(<8 x i16> %0, ptr %next.gep20, i32 2, <8 x i1> %active.lane.…
83 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %blockSize)
84 …all <8 x i16> @llvm.masked.load.v8i16.p0(ptr %next.gep, i32 2, <8 x i1> %active.lane.mask, <8 x i1…
85 …l <8 x i16> @llvm.masked.load.v8i16.p0(ptr %next.gep21, i32 2, <8 x i1> %active.lane.mask, <8 x i1…
87 …call void @llvm.masked.store.v8i16.p0(<8 x i16> %0, ptr %next.gep20, i32 2, <8 x i1> %active.lane.…
96 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
H A Dtail-pred-intrinsic-add-sat.ll37 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %blockSize)
38 …all <8 x i16> @llvm.masked.load.v8i16.p0(ptr %next.gep, i32 2, <8 x i1> %active.lane.mask, <8 x i1…
39 …l <8 x i16> @llvm.masked.load.v8i16.p0(ptr %next.gep21, i32 2, <8 x i1> %active.lane.mask, <8 x i1…
41 …call void @llvm.masked.store.v8i16.p0(<8 x i16> %0, ptr %next.gep20, i32 2, <8 x i1> %active.lane.…
83 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %blockSize)
84 …all <8 x i16> @llvm.masked.load.v8i16.p0(ptr %next.gep, i32 2, <8 x i1> %active.lane.mask, <8 x i1…
85 …l <8 x i16> @llvm.masked.load.v8i16.p0(ptr %next.gep21, i32 2, <8 x i1> %active.lane.mask, <8 x i1…
87 …call void @llvm.masked.store.v8i16.p0(<8 x i16> %0, ptr %next.gep20, i32 2, <8 x i1> %active.lane.…
96 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
H A Dreductions.ll39 %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 %index, i32 %N)
41 …%wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %i1, i32 1, <16 x i1> %active.la…
44 …%wide.masked.load16 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %i3, i32 1, <16 x i1> %active.…
46 %i5 = select <16 x i1> %active.lane.mask, <16 x i8> %i4, <16 x i8> %vec.phi
107 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %N)
109 …%wide.masked.load = call <8 x i8> @llvm.masked.load.v8i8.p0(ptr %i1, i32 1, <8 x i1> %active.lane.…
113 …%wide.masked.load17 = call <8 x i8> @llvm.masked.load.v8i8.p0(ptr %i4, i32 1, <8 x i1> %active.lan…
122 %i9 = select <8 x i1> %active.lane.mask, <8 x i16> %i7, <8 x i16> %vec.phi
178 %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 %index, i32 %N)
180 …%wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %i1, i32 1, <16 x i1> %active.la…
[all …]
/llvm-project/libc/src/__support/threads/
H A Dthread.cpp34 // Indicates whether is unit is active. Presence of a non-null dtor
37 bool active = false;
42 constexpr TSSKeyUnit(TSSDtor *d) : active(true), dtor(d) {}
45 active = false;
63 if (!u.active) { in new_key()
88 return units[key].active; in is_valid_key()
95 bool active = false;
101 : active(true), payload(p), dtor(d) {}
186 if (!u.active) in get_tss_value()
39 bool active = false; global() member
97 bool active = false; global() member
/llvm-project/llvm/test/Verifier/
H A Dget-active-lane-mask.ll3 declare <4 x i32> @llvm.get.active.lane.mask.v4i32.i32(i32, i32)
7 ; CHECK-NEXT: %res = call <4 x i32> @llvm.get.active.lane.mask.v4i32.i32(i32 %IV, i32 %TC)
9 %res = call <4 x i32> @llvm.get.active.lane.mask.v4i32.i32(i32 %IV, i32 %TC)
13 declare i32 @llvm.get.active.lane.mask.i32.i32(i32, i32)
17 ; CHECK-NEXT: ptr @llvm.get.active.lane.mask.i32.i32
19 %res = call i32 @llvm.get.active.lane.mask.i32.i32(i32 %IV, i32 %TC)
/llvm-project/llvm/test/Transforms/LoopVectorize/ARM/
H A Dtail-folding-prefer-flag.ll25 ; PREDFLAG: %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 %[[ELEM0]], i64 430)
26 ; PREDFLAG: %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0({{.*}}, <4 x i1> %active.lane.mask
27 ; PREDFLAG: %wide.masked.load1 = call <4 x i32> @llvm.masked.load.v4i32.p0({{.*}}, <4 x i1> %active.lane.mask
29 ; PREDFLAG: call void @llvm.masked.store.v4i32.p0({{.*}}, <4 x i1> %active.lane.mask
59 ; PREDFLAG: %[[ALM1:active.lane.mask.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %[[ADD1]], i32 %N)
60 ; PREDFLAG: %[[ALM2:active.lane.mask.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %[[ADD2]], i32 %N)
61 ; PREDFLAG: %[[ALM3:active
[all...]
/llvm-project/llvm/test/CodeGen/Thumb2/
H A Dmve-vmaxnma-tailpred.ll35 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n)
37 …%wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0(ptr %0, i32 4, <4 x i1> %active.la…
40 …%wide.masked.load10 = call <4 x float> @llvm.masked.load.v4f32.p0(ptr %2, i32 4, <4 x i1> %active.…
43 call void @llvm.masked.store.v4f32.p0(<4 x float> %3, ptr %4, i32 4, <4 x i1> %active.lane.mask)
82 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n)
84 …%wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0(ptr %0, i32 4, <4 x i1> %active.la…
87 …%wide.masked.load10 = call <4 x float> @llvm.masked.load.v4f32.p0(ptr %2, i32 4, <4 x i1> %active.…
91 call void @llvm.masked.store.v4f32.p0(<4 x float> %4, ptr %5, i32 4, <4 x i1> %active.lane.mask)
132 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %n)
134 …%wide.masked.load = call <8 x half> @llvm.masked.load.v8f16.p0(ptr %0, i32 2, <8 x i1> %active.lan…
[all …]
H A Dactive_lane_mask.ll52 %active.lane.mask = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 %index, i32 %TC)
53 %select = select <2 x i1> %active.lane.mask, <2 x i64> %V1, <2 x i64> %V2
80 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %TC)
81 %select = select <4 x i1> %active.lane.mask, <4 x i32> %V1, <4 x i32> %V2
141 %active.lane.mask = call <7 x i1> @llvm.get.active.lane.mask.v7i1.i32(i32 %index, i32 %TC)
142 %select = select <7 x i1> %active.lane.mask, <7 x i32> %V1, <7 x i32> %V2
190 %active.lane.mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 %index, i32 %TC)
191 %select = select <8 x i1> %active.lane.mask, <8 x i16> %V1, <8 x i16> %V2
271 %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 %index, i32 %TC)
272 %select = select <16 x i1> %active.lane.mask, <16 x i8> %V1, <16 x i8> %V2
[all …]
H A Dmve-gather-scatter-tailpred.ll44 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n)
46 …%wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %2, i32 4, <4 x i1> %active.lane…
50 … <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %5, i32 4, <4 x i1> %active.lane.mask, <4 x i3…
58 %9 = select <4 x i1> %active.lane.mask, <4 x i32> %7, <4 x i32> %vec.phi
113 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n)
115 …%wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %2, i32 4, <4 x i1> %active.lane…
119 … <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %5, i32 4, <4 x i1> %active.lane.mask, <4 x i3…
121 …call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %6, <4 x ptr> %5, i32 4, <4 x i1> %active.lane…
128 %9 = select <4 x i1> %active.lane.mask, <4 x i32> %7, <4 x i32> %vec.phi
183 %active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %n)
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/llvm-project/openmp/runtime/src/
H A Dkmp_dispatch_hier.h336 kmp_int32 active; // number of topology units that communicate with this unit member
344 KMP_DEBUG_ASSERT(active > 0); in reset_shared_barrier()
345 if (active == 1) in reset_shared_barrier()
348 if (active >= 2 && active <= 8) { in reset_shared_barrier()
349 core_barrier_impl<T>::reset_shared(active, &hier_barrier); in reset_shared_barrier()
351 counter_barrier_impl<T>::reset_shared(active, &hier_barrier); in reset_shared_barrier()
356 KMP_DEBUG_ASSERT(active > 0); in reset_private_barrier()
357 if (active == 1) in reset_private_barrier()
359 if (active >= 2 && active <= 8) { in reset_private_barrier()
360 core_barrier_impl<T>::reset_private(active, tdata); in reset_private_barrier()
[all …]
/llvm-project/libcxx/test/support/
H A Dformat_string.h15 bool active; in format_string_imp() member
16 GuardVAList(va_list& val) : xtarget(val), active(true) {} in format_string_imp()
19 if (active) in format_string_imp()
21 active = false; in format_string_imp()
24 if (active) in format_string_imp()
/llvm-project/llvm/test/CodeGen/X86/
H A Dpr47299.ll4 declare <7 x i1> @llvm.get.active.lane.mask.v7i1.i64(i64, i64)
5 declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64, i64)
6 declare <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64, i64)
7 declare <64 x i1> @llvm.get.active.lane.mask.v64i1.i64(i64, i64)
8 declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32)
9 declare <64 x i1> @llvm.get.active.lane.mask.v64i1.i32(i32, i32)
52 %2 = call <7 x i1> @llvm.get.active.lane.mask.v7i1.i64(i64 0, i64 %0)
66 %2 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 0, i64 %0)
83 %2 = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64 0, i64 %0)
108 %2 = call <64 x i1> @llvm.get.active.lane.mask.v64i1.i64(i64 0, i64 %0)
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/llvm-project/clang/docs/
H A DItaniumMangleAbiTags.rst30 All tags that are "active" on an <unqualified-name> are emitted after the
52 A namespace does not have any active tags. For types (class / struct / union /
53 enum), the explicit tags are the active tags.
55 For variables and functions, the active tags are the explicit tags plus any
61 active-tags := explicit-tags + derived-tags
99 For <local-name>s all active tags used in the local part (<function-
100 encoding>) are available, but not implicit tags which were not active.
106 std::__cxx11::basic_string<...>) will use 'cxx11' as an active tag, as it is
/llvm-project/libcxx/test/std/strings/basic.string/string.cons/
H A Dcopy_alloc.pass.cpp23 bool active; member
25 TEST_CONSTEXPR alloc_imp() : active(true) {} in alloc_imp()
29 if (active) in allocate()
39 void activate() { active = true; } in activate()
40 void deactivate() { active = false; } in deactivate()
/llvm-project/llvm/test/CodeGen/RISCV/rvv/
H A Dactive_lane_mask.ll12 %mask = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i64(i64 %index, i64 %tc)
23 %mask = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i64(i64 0, i64 %tc)
36 %mask = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i64(i64 24, i64 %tc)
49 %mask = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i64(i64 %index, i64 1024)
61 %mask = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i64(i64 0, i64 1024)
75 %mask = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i64(i64 0, i64 2048)
87 %mask = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64 %index, i64 %tc)
99 %mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 %index, i64 %tc)
119 %mask = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64 %index, i64 %tc)
156 %mask = call <64 x i1> @llvm.get.active
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