Home
last modified time | relevance | path

Searched refs:StackPtr (Results 1 – 25 of 49) sorted by relevance

12

/llvm-project/llvm/lib/Target/X86/
H A DX86DynAllocaExpander.cpp60 unsigned StackPtr = 0;
159 // A DynAlloca moves StackPtr, and potentially touches it. in computeLowerings()
183 } else if (MI.modifiesRegister(StackPtr, TRI)) { in computeLowerings()
246 BuildMI(*MBB, I, DL, TII->get(getSubOpcode(Is64BitAlloca)), StackPtr) in lower()
247 .addReg(StackPtr) in lower()
264 TII->get(Is64BitAlloca ? X86::SUB64rr : X86::SUB32rr), StackPtr) in lower()
265 .addReg(StackPtr) in lower()
288 StackPtr = TRI->getStackRegister(); in runOnMachineFunction()
62 unsigned StackPtr = 0; global() member in __anona6af4fc20111::X86DynAllocaExpander
H A DX86FrameLowering.cpp59 StackPtr = TRI->getStackRegister(); in X86FrameLowering()
279 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AddSubRROpc), StackPtr) in emitSPUpdate()
280 .addReg(StackPtr) in emitSPUpdate()
308 .addReg(StackPtr); in emitSPUpdate()
313 StackPtr, false, 0); in emitSPUpdate()
315 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), StackPtr), in emitSPUpdate()
316 StackPtr, false, 0); in emitSPUpdate()
379 StackPtr), in BuildStackAdjustment()
380 StackPtr, false, Offset); in BuildStackAdjustment()
386 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) in mergeSPUpdates()
[all...]
H A DX86RegisterInfo.h38 /// StackPtr - X86 physical register used as stack ptr.
40 unsigned StackPtr; variable
165 Register getStackRegister() const { return StackPtr; } in getStackRegister()
H A DX86CallFrameOptimization.cpp383 Register StackPtr = RegInfo.getStackRegister(); in collectCallInfo() local
395 J->getOperand(1).getReg() == StackPtr) { in collectCallInfo()
398 StackPtr = Context.SPCopy->getOperand(0).getReg(); in collectCallInfo()
428 (I->getOperand(X86::AddrBaseReg).getReg() != StackPtr) || in collectCallInfo()
H A DX86RegisterInfo.cpp73 StackPtr = Use64BitReg ? X86::RSP : X86::ESP; in X86RegisterInfo()
78 StackPtr = X86::ESP;
955 if (BasePtr == StackPtr) in eliminateFrameIndex()
1034 return TFI->hasFP(MF) ? FramePtr : StackPtr;
H A DX86ISelLoweringCall.cpp1931 SDValue X86TargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, in LowerMemOpCallTo()
1940 StackPtr, PtrOff); in LowerMemOpCallTo()
2151 SDValue StackPtr; in LowerCall()
2252 if (!StackPtr.getNode()) in LowerCall()
2253 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(), in LowerCall()
2255 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, in LowerCall()
2370 if (!StackPtr.getNode()) in LowerCall()
2371 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(), in LowerCall()
2374 StackPtr, Source); in LowerCall()
1923 LowerMemOpCallTo(SDValue Chain,SDValue StackPtr,SDValue Arg,const SDLoc & dl,SelectionDAG & DAG,const CCValAssign & VA,ISD::ArgFlagsTy Flags,bool isByVal) const LowerMemOpCallTo() argument
2143 SDValue StackPtr; LowerCall() local
H A DX86FrameLowering.h47 /// instruction operands should be used to manipulate StackPtr and FramePtr.
50 unsigned StackPtr; variable
/llvm-project/llvm/lib/Target/M68k/
H A DM68kRegisterInfo.cpp49 StackPtr = M68k::SP; in M68kRegisterInfo()
187 BasePtr = (FIndex < 0 ? FramePtr : StackPtr); in eliminateFrameIndex()
189 BasePtr = StackPtr; in eliminateFrameIndex()
191 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr); in eliminateFrameIndex()
207 if (BasePtr == StackPtr) in eliminateFrameIndex()
264 return TFI->hasFP(MF) ? FramePtr : StackPtr; in getFrameRegister()
H A DM68kFrameLowering.cpp42 StackPtr = TRI->getStackRegister();
361 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) in emitSPUpdate()
362 .addReg(StackPtr) in emitSPUpdate()
403 if (Opc == M68k::ADD32ai && PI->getOperand(0).getReg() == StackPtr) { in mergeSPUpdates()
404 assert(PI->getOperand(1).getReg() == StackPtr); in mergeSPUpdates()
409 } else if (Opc == M68k::SUB32ai && PI->getOperand(0).getReg() == StackPtr) { in mergeSPUpdates()
410 assert(PI->getOperand(1).getReg() == StackPtr); in mergeSPUpdates()
431 MachineInstrBuilder MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) in BuildStackAdjustment()
432 .addReg(StackPtr) in BuildStackAdjustment()
605 BuildStackAlignAND(MBB, MBBI, DL, StackPtr, MaxAlig in emitPrologue()
[all...]
H A DM68kRegisterInfo.h34 unsigned StackPtr; variable
108 unsigned getStackRegister() const { return StackPtr; } in getStackRegister()
H A DM68kFrameLowering.h37 unsigned StackPtr; variable
/llvm-project/compiler-rt/lib/fuzzer/
H A DFuzzerUtilFuchsia.cpp345 uintptr_t StackPtr = in CrashHandler() local
348 __unsanitized_memcpy(reinterpret_cast<void *>(StackPtr), &GeneralRegisters, in CrashHandler()
350 GeneralRegisters.rsp = StackPtr; in CrashHandler()
355 uintptr_t StackPtr = in CrashHandler() local
357 __unsanitized_memcpy(reinterpret_cast<void *>(StackPtr), &GeneralRegisters, in CrashHandler()
359 GeneralRegisters.sp = StackPtr; in CrashHandler()
/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp165 SDValue StackPtr = DAG.CreateStackTemporary(InVT.getStoreSize(), Align); in ExpandRes_BITCAST() local
166 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); in ExpandRes_BITCAST()
171 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, StackPtr, PtrInfo); in ExpandRes_BITCAST()
174 Lo = DAG.getLoad(NOutVT, dl, Store, StackPtr, PtrInfo, NOutAlign); in ExpandRes_BITCAST()
178 StackPtr = in ExpandRes_BITCAST()
179 DAG.getMemBasePlusOffset(StackPtr, TypeSize::getFixed(IncrementSize), dl); in ExpandRes_BITCAST()
182 Hi = DAG.getLoad(NOutVT, dl, Store, StackPtr, in ExpandRes_BITCAST()
H A DLegalizeDAG.cpp263 static MachineMemOperand *getStackAlignedMMO(SDValue StackPtr,
267 int FI = cast<FrameIndexSDNode>(StackPtr)->getIndex(); in getStackAlignedMMO()
1396 SDValue StackPtr, Ch; in ExpandExtractFromVectorThroughStack()
1417 StackPtr = ST->getBasePtr(); in ExpandExtractFromVectorThroughStack()
1427 StackPtr = DAG.CreateStackTemporary(VecVT); in ExpandExtractFromVectorThroughStack()
1429 StackPtr, DAG.getMachineFunction(), VecVT.isScalableVector()); in ExpandExtractFromVectorThroughStack()
1430 Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, StoreMMO); in ExpandExtractFromVectorThroughStack()
1440 StackPtr = TLI.getVectorSubVecPointer(DAG, StackPtr, VecVT, in ExpandExtractFromVectorThroughStack()
1442 NewLoad = DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, in ExpandExtractFromVectorThroughStack()
264 getStackAlignedMMO(SDValue StackPtr,MachineFunction & MF,bool isObjectScalable) getStackAlignedMMO() argument
1392 SDValue StackPtr, Ch; ExpandExtractFromVectorThroughStack() local
1471 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); ExpandInsertToVectorThroughStack() local
1585 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy); getSignAsIntValue() local
1827 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); ExpandSCALAR_TO_VECTOR() local
4994 SDValue StackPtr = DAG.CreateStackTemporary(ModeVT); ConvertNodeToLibcall() local
5010 SDValue StackPtr = DAG.CreateStackTemporary(ModeVT); ConvertNodeToLibcall() local
[all...]
H A DLegalizeTypes.cpp904 SDValue StackPtr = in CreateStackStoreLoad()
907 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op, StackPtr, in CreateStackStoreLoad()
910 return DAG.getLoad(DestVT, dl, Store, StackPtr, MachinePointerInfo(), Align); in CreateStackStoreLoad()
905 SDValue StackPtr = CreateStackStoreLoad() local
H A DLegalizeVectorTypes.cpp1675 SDValue StackPtr = in SplitVecRes_IS_FPCLASS()
1678 auto FrameIndex = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); in SplitVecRes_InregOp()
1681 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo, in SplitVecRes_InregOp()
1686 TLI.getVectorSubVecPointer(DAG, StackPtr, VecVT, SubVecVT, Idx); in SplitVecRes_InregOp()
1691 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, PtrInfo, in SplitVecRes_InregOp()
1697 IncrementPointer(Load, LoVT, MPI, StackPtr); in SplitVecRes_ExtVecInRegOp()
1700 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MPI, SmallestAlign); in SplitVecRes_ExtVecInRegOp()
1988 SDValue StackPtr = in SplitVecRes_ScalarOp()
1991 auto FrameIndex = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); in SplitVecRes_ScalarOp()
1994 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInf in SplitVecRes_ScalarOp()
1607 SDValue StackPtr = SplitVecRes_INSERT_SUBVECTOR() local
1920 SDValue StackPtr = SplitVecRes_INSERT_VECTOR_ELT() local
3004 SDValue StackPtr = DAG.CreateStackTemporary(MemVT.getStoreSize(), Alignment); SplitVecRes_VP_REVERSE() local
3477 SDValue StackPtr = SplitVecOp_EXTRACT_SUBVECTOR() local
3535 SDValue StackPtr = SplitVecOp_EXTRACT_VECTOR_ELT() local
[all...]
/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp484 SDValue StackPtr; in LowerReturn()
500 if (!StackPtr.getNode()) in LowerReturn()
501 StackPtr = DAG.getCopyFromReg(Chain, DL, Xtensa::SP, PtrVT); in LowerReturn()
503 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, in LowerReturn()
517 if (!StackPtr.getNode()) in LowerImmediate()
518 StackPtr = DAG.getCopyFromReg(Chain, DL, Xtensa::SP, PtrVT); in LowerImmediate()
520 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, in LowerImmediate()
950 SDValue StackPtr = DAG.getNode(ISD::SUB, DL, PtrVT, StackOffsetFI,
954 DAG.getStore(Chain, DL, StackPtr, Addr, MachinePointerInfo(SV));
326 SDValue StackPtr; LowerCall() local
/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp299 SDValue StackPtr; in LowerCall() local
328 if (!StackPtr.getNode()) in LowerCall()
329 StackPtr = DAG.getCopyFromReg(Chain, dl, ARC::SP, in LowerCall()
334 ISD::ADD, dl, getPointerTy(DAG.getDataLayout()), StackPtr, SOffset); in LowerCall()
438 SDValue StackPtr = DAG.getRegister(ARC::SP, MVT::i32); in lowerCallResult() local
439 SDValue SpLoc = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, in lowerCallResult()
H A DARCFrameLowering.cpp47 int Amount, int StackPtr) { in generateStackAdjustment() argument
72 BuildMI(MBB, MBBI, dl, TII.get(AdjOp), StackPtr) in generateStackAdjustment()
73 .addReg(StackPtr) in generateStackAdjustment()
/llvm-project/llvm/lib/CodeGen/
H A DSjLjEHPrepare.cpp425 Value *StackPtr = Builder.CreateConstGEP2_32(doubleUnderJBufTy, JBufPtr, 0, 2, in setupEntryBlockAndCallSites() local
429 Builder.CreateStore(Val, StackPtr, /*isVolatile=*/true); in setupEntryBlockAndCallSites()
482 new StoreInst(StackAddr, StackPtr, true, in setupEntryBlockAndCallSites()
/llvm-project/llvm/lib/DebugInfo/CodeView/
H A DSymbolRecordMapping.cpp516 case EncodedFramePtrReg::StackPtr: return RegisterId::VFRAME; in decodeFramePtrReg()
524 case EncodedFramePtrReg::StackPtr: return RegisterId::RSP; in decodeFramePtrReg()
548 return EncodedFramePtrReg::StackPtr; in encodeFramePtrReg()
560 return EncodedFramePtrReg::StackPtr; in encodeFramePtrReg()
/llvm-project/llvm/lib/Target/ARM/
H A DREADME.txt330 int foo(int StackPtr, unsigned char *Line, unsigned char *Stack, int LineLen) {
333 if (StackPtr != 0) {
334 while (StackPtr != 0 && i < (((LineLen) < (32768))? (LineLen) : (32768)))
335 Line[i++] = Stack[--StackPtr];
338 while (StackPtr != 0 && i < LineLen)
341 --StackPtr;
345 return StackPtr;
/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp571 SDValue StackPtr; in LowerCall()
592 if (!StackPtr.getNode()) in LowerCall()
593 StackPtr = DAG.getCopyFromReg(Chain, DL, CSKY::R14, PtrVT); in LowerCall()
596 DAG.getStore(Chain, DL, Hi, StackPtr, MachinePointerInfo())); in LowerCall()
621 if (!StackPtr.getNode()) in LowerCall()
622 StackPtr = DAG.getCopyFromReg(Chain, DL, CSKY::R14, PtrVT); in LowerCall()
624 DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, in LowerCall()
570 SDValue StackPtr; LowerCall() local
/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp935 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32() local
937 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
955 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32() local
957 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
989 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32() local
991 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
998 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32() local
1000 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
1005 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
1027 SDValue StackPtr in LowerCall_32() local
1307 SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT); LowerCall_64() local
1362 SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT); LowerCall_64() local
[all...]
/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.h616 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
635 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,

12