Lines Matching refs:StackPtr
59 StackPtr = TRI->getStackRegister();
279 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AddSubRROpc), StackPtr)
280 .addReg(StackPtr)
308 .addReg(StackPtr);
313 StackPtr, false, 0);
315 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), StackPtr),
316 StackPtr, false, 0);
379 StackPtr),
380 StackPtr, false, Offset);
386 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
387 .addReg(StackPtr)
422 PI->getOperand(0).getReg() == StackPtr) {
423 assert(PI->getOperand(1).getReg() == StackPtr);
426 PI->getOperand(0).getReg() == StackPtr &&
427 PI->getOperand(1).getReg() == StackPtr &&
434 PI->getOperand(0).getReg() == StackPtr) {
435 assert(PI->getOperand(1).getReg() == StackPtr);
717 StackPtr, false, 0)
738 StackPtr, false, 0)
788 StackPtr, false, 0)
825 .addReg(StackPtr)
837 .addReg(StackPtr)
869 StackPtr, false, 0)
875 .addReg(StackPtr)
907 ? Register(getX86SubSuperRegister(StackPtr, 64))
908 : Register(StackPtr);
1296 if (Reg == StackPtr && EmitInlineStackProbe && MaxAlign >= StackProbeSize) {
1323 .addReg(StackPtr)
1337 .addReg(StackPtr)
1351 BuildMI(headMBB, DL, TII.get(SUBOpc), StackPtr)
1352 .addReg(StackPtr)
1358 .addReg(StackPtr)
1362 // jump to the footer if StackPtr < FinalStackProbed
1376 StackPtr, false, 0)
1381 BuildMI(bodyMBB, DL, TII.get(SUBOpc), StackPtr)
1382 .addReg(StackPtr)
1390 .addReg(StackPtr)
1393 // jump back while FinalStackProbed < StackPtr
1404 BuildMI(footMBB, DL, TII.get(TargetOpcode::COPY), StackPtr)
1409 StackPtr, false, 0)
1610 .addUse(StackPtr)
1623 BuildStackAlignAND(MBB, MBBI, DL, StackPtr, MaxAlign);
1757 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MOVmr)), StackPtr, true, 16)
1856 .addReg(StackPtr)
1966 BuildStackAlignAND(MBB, MBBI, DL, StackPtr, MaxAlign);
2038 StackPtr, false, NumBytes - 8);
2041 StackPtr, false, NumBytes - 4);
2074 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mr)), StackPtr,
2084 SPOrEstablisher = StackPtr;
2166 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mr)), StackPtr, false,
2168 .addReg(StackPtr)
2560 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr), FramePtr,
2565 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr).addReg(FramePtr);
3996 return StackPtr;
4324 Register StackPtr = TRI->getStackRegister();
4326 StackPtr = Register(getX86SubSuperRegister(StackPtr, 64));
4327 unsigned DwarfStackPtr = TRI->getDwarfRegNum(StackPtr, true);