| /llvm-project/llvm/test/TableGen/ |
| H A D | BitOffsetDecoder.td | 25 field bits<16> SoftFail = 0; 35 field bits<16> SoftFail = 0; 45 field bits<16> SoftFail = 0; 55 field bits<16> SoftFail = 0;
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| H A D | BigEncoder.td | 25 field bits<16> SoftFail = 0; 35 field bits<16> SoftFail = 0; 45 field bits<16> SoftFail = 0;
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| H A D | get-operand-type.td | 26 field bits<8> SoftFail = 0; 35 field bits<8> SoftFail = 0; 44 field bits<8> SoftFail = 0;
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| H A D | HwModeEncodeDecode2.td | 29 field bits<32> SoftFail = 0; 39 field bits<32> SoftFail = 0; 63 bits<32> SoftFail; 88 bits<32> SoftFail;
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| H A D | HwModeEncodeAPInt.td | 27 field bits<128> SoftFail = 0; 37 field bits<128> SoftFail = 0; 47 field bits<128> SoftFail = 0; 56 field bits<128> SoftFail = 0; 80 bits<32> SoftFail; 103 bits<32> SoftFail;
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| H A D | HwModeEncodeDecode.td | 25 field bits<32> SoftFail = 0; 35 field bits<32> SoftFail = 0; 56 bits<32> SoftFail;
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| H A D | HwModeEncodeDecode3.td | 32 field bits<64> SoftFail = 0; 42 field bits<32> SoftFail = 0; 52 field bits<32> SoftFail = 0; 61 field bits<32> SoftFail = 0; 84 bits<32> SoftFail; 107 bits<32> SoftFail;
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| H A D | AsmPredicateCombiningRISCV.td | 32 field bits<32> SoftFail = 0; 42 field bits<16> SoftFail = 0;
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| H A D | AsmPredicateCondsEmission.td | 27 field bits<16> SoftFail = 0;
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| H A D | trydecode-emission3.td | 16 field bits<8> SoftFail = 0;
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| H A D | def-multiple-operands.td | 35 field bits<8> SoftFail = 0;
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| H A D | trydecode-emission4.td | 20 field bits<512> SoftFail = 0;
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| H A D | trydecode-emission2.td | 16 field bits<8> SoftFail = 0;
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| H A D | trydecode-emission.td | 21 field bits<8> SoftFail = 0;
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| H A D | HwModeBitSet.td | 94 field bits<64> SoftFail = 0; 104 field bits<32> SoftFail = 0;
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| H A D | get-operand-type-no-expand.td | 28 field bits<8> SoftFail = 0;
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| /llvm-project/llvm/test/TableGen/FixedLenDecoderEmitter/ |
| H A D | InitValue.td | 16 field bits<16> SoftFail = 0; 25 field bits<16> SoftFail = 0; 34 field bits<16> SoftFail = 0;
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| H A D | conflict.td | 19 bits<32> SoftFail;
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| /llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 728 return MCDisassembler::SoftFail; in checkDecodedInstruction() 741 return MCDisassembler::SoftFail; in checkDecodedInstruction() 945 S = SoftFail; in AddThumbPredicate() 951 S = SoftFail; in AddThumbPredicate() 960 S = SoftFail; in AddThumbPredicate() 970 S = SoftFail; in AddThumbPredicate() 1000 Check(S, SoftFail); in AddThumbPredicate() 1028 Check(S, SoftFail); in AddThumbPredicate() 1059 Check(S, SoftFail); in UpdateThumbVFPPredicate() 1114 Result = MCDisassembler::SoftFail; in getThumbInstruction() [all...] |
| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrFormats.td | 191 field bits<16> SoftFail = 0; 199 field bits<16> SoftFail = 0; 210 field bits<32> SoftFail = 0; 224 field bits<48> SoftFail = 0; 239 field bits<32> SoftFail = 0; 253 field bits<32> SoftFail = 0; 267 field bits<32> SoftFail = 0; 281 field bits<48> SoftFail = 0; 299 field bits<48> SoftFail = 0; 318 field bits<48> SoftFail [all...] |
| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrFormats.td | 63 // SoftFail is a field the disassembler can use to provide a way for 67 field bits<32> SoftFail = 0; 290 // SoftFail is a field the disassembler can use to provide a way for 294 field bits<32> SoftFail = 0;
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| /llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaInstrFormats.td | 33 field bits<24> SoftFail = 0; 41 field bits<16> SoftFail = 0;
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| /llvm-project/llvm/include/llvm/MC/MCDisassembler/ |
| H A D | MCDisassembler.h | 110 SoftFail = 1, enumerator
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| /llvm-project/llvm/tools/llvm-mc/ |
| H A D | Disassembler.cpp | 63 case MCDisassembler::SoftFail: in PrintInsts()
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| /llvm-project/llvm/tools/llvm-ml/ |
| H A D | Disassembler.cpp | 60 case MCDisassembler::SoftFail: in PrintInsts()
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