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Searched refs:dev_priv (Results 1 – 25 of 117) sorted by relevance

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/dflybsd-src/sys/dev/drm/i915/
H A Di915_drv.c82 __i915_printk(struct drm_i915_private *dev_priv, const char *level, in __i915_printk() argument
86 struct device *kdev = dev_priv->drm.dev; in __i915_printk()
111 static bool i915_error_injected(struct drm_i915_private *dev_priv) in i915_error_injected() argument
117 #define i915_load_error(dev_priv, fmt, ...) \ argument
118 __i915_printk(dev_priv, \
119 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
123 static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv) in intel_virt_detect_pch() argument
134 if (IS_GEN5(dev_priv)) { in intel_virt_detect_pch()
137 } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) { in intel_virt_detect_pch()
140 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { in intel_virt_detect_pch()
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H A Dintel_uncore.c157 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) in __gen6_gt_wait_for_thread_c0() argument
162 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & in __gen6_gt_wait_for_thread_c0()
167 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv, in fw_domains_get_with_thread_status() argument
170 fw_domains_get(dev_priv, fw_domains); in fw_domains_get_with_thread_status()
173 __gen6_gt_wait_for_thread_c0(dev_priv); in fw_domains_get_with_thread_status()
176 static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv) in fifo_free_entries() argument
178 u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL); in fifo_free_entries()
183 static void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) in __gen6_gt_wait_for_fifo() argument
189 if (IS_VALLEYVIEW(dev_priv)) in __gen6_gt_wait_for_fifo()
190 n = fifo_free_entries(dev_priv); in __gen6_gt_wait_for_fifo()
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H A Di915_irq.c152 static void gen3_assert_iir_is_zero(struct drm_i915_private *dev_priv, in gen3_assert_iir_is_zero() argument
168 static void gen2_assert_iir_is_zero(struct drm_i915_private *dev_priv, in gen2_assert_iir_is_zero() argument
185 gen3_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
192 gen3_assert_iir_is_zero(dev_priv, type##IIR); \
199 gen2_assert_iir_is_zero(dev_priv, type##IIR); \
205 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
206 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
210 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv, in i915_hotplug_interrupt_update_locked() argument
216 lockdep_assert_held(&dev_priv->irq_lock); in i915_hotplug_interrupt_update_locked()
237 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, in i915_hotplug_interrupt_update() argument
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H A Dintel_cdclk.c54 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_133mhz_get_cdclk() argument
60 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_200mhz_get_cdclk() argument
66 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_266mhz_get_cdclk() argument
72 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_333mhz_get_cdclk() argument
78 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_400mhz_get_cdclk() argument
84 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_450mhz_get_cdclk() argument
90 static void i85x_get_cdclk(struct drm_i915_private *dev_priv, in i85x_get_cdclk() argument
93 struct pci_dev *pdev = dev_priv->drm.pdev; in i85x_get_cdclk()
132 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, in i915gm_get_cdclk() argument
135 struct pci_dev *pdev = dev_priv->drm.pdev; in i915gm_get_cdclk()
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H A Di915_perf.c352 static bool gen7_oa_buffer_is_empty_fop_unlocked(struct drm_i915_private *dev_priv)
354 int report_size = dev_priv->perf.oa.oa_buffer.format_size;
361 dev_priv->perf.oa.tail_margin + report_size;
421 struct drm_i915_private *dev_priv = stream->dev_priv;
422 int report_size = dev_priv->perf.oa.oa_buffer.format_size;
473 struct drm_i915_private *dev_priv = stream->dev_priv;
474 int report_size = dev_priv->perf.oa.oa_buffer.format_size;
475 u8 *oa_buf_base = dev_priv->perf.oa.oa_buffer.vaddr;
476 u32 gtt_offset = i915_ggtt_offset(dev_priv->perf.oa.oa_buffer.vma);
488 spin_lock_irqsave(&dev_priv->perf.oa.oa_buffer.ptr_lock, flags);
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H A Dintel_psr.c69 struct drm_i915_private *dev_priv = to_i915(dev); in vlv_is_psr_active_on_pipe() local
82 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_psr_setup_vsc() local
96 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); in hsw_psr_setup_vsc() local
99 if (dev_priv->psr.psr2_support) { in hsw_psr_setup_vsc()
104 if (dev_priv->psr.colorimetry_support && in hsw_psr_setup_vsc()
105 dev_priv->psr.y_cord_support) { in hsw_psr_setup_vsc()
108 } else if (dev_priv->psr.y_cord_support) { in hsw_psr_setup_vsc()
134 static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv, in psr_aux_ctl_reg() argument
137 if (INTEL_INFO(dev_priv)->gen >= 9) in psr_aux_ctl_reg()
143 static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv, in psr_aux_data_reg() argument
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H A Di915_suspend.c32 static void i915_save_display(struct drm_i915_private *dev_priv) in i915_save_display() argument
35 if (INTEL_GEN(dev_priv) <= 4) in i915_save_display()
36 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB); in i915_save_display()
39 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) in i915_save_display()
40 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL); in i915_save_display()
43 static void i915_restore_display(struct drm_i915_private *dev_priv) in i915_restore_display() argument
46 if (INTEL_GEN(dev_priv) <= 4) in i915_restore_display()
47 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB); in i915_restore_display()
50 intel_fbc_global_disable(dev_priv); in i915_restore_display()
53 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) in i915_restore_display()
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H A Dintel_runtime_pm.c52 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
56 lookup_power_well(struct drm_i915_private *dev_priv,
139 static void intel_power_well_enable(struct drm_i915_private *dev_priv, in intel_power_well_enable() argument
143 power_well->ops->enable(dev_priv, power_well); in intel_power_well_enable()
147 static void intel_power_well_disable(struct drm_i915_private *dev_priv, in intel_power_well_disable() argument
152 power_well->ops->disable(dev_priv, power_well); in intel_power_well_disable()
155 static void intel_power_well_get(struct drm_i915_private *dev_priv, in intel_power_well_get() argument
159 intel_power_well_enable(dev_priv, power_well); in intel_power_well_get()
162 static void intel_power_well_put(struct drm_i915_private *dev_priv, in intel_power_well_put() argument
169 intel_power_well_disable(dev_priv, power_well); in intel_power_well_put()
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H A Dintel_fbc.c44 static inline bool fbc_supported(struct drm_i915_private *dev_priv) in fbc_supported() argument
46 return HAS_FBC(dev_priv); in fbc_supported()
49 static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv) in fbc_on_pipe_a_only() argument
51 return IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8; in fbc_on_pipe_a_only()
54 static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv) in fbc_on_plane_a_only() argument
56 return INTEL_GEN(dev_priv) < 4; in fbc_on_plane_a_only()
59 static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv) in no_fbc_on_multiple_pipes() argument
61 return INTEL_GEN(dev_priv) <= 3; in no_fbc_on_multiple_pipes()
91 static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv, in intel_fbc_calculate_cfb_size() argument
97 if (INTEL_GEN(dev_priv) == 7) in intel_fbc_calculate_cfb_size()
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H A Dintel_hotplug.c152 static bool intel_hpd_irq_storm_detect(struct drm_i915_private *dev_priv, in intel_hpd_irq_storm_detect() argument
155 unsigned long start = dev_priv->hotplug.stats[pin].last_jiffies; in intel_hpd_irq_storm_detect()
157 const int threshold = dev_priv->hotplug.hpd_storm_threshold; in intel_hpd_irq_storm_detect()
161 dev_priv->hotplug.stats[pin].last_jiffies = jiffies; in intel_hpd_irq_storm_detect()
162 dev_priv->hotplug.stats[pin].count = 0; in intel_hpd_irq_storm_detect()
164 } else if (dev_priv->hotplug.stats[pin].count > threshold && in intel_hpd_irq_storm_detect()
166 dev_priv->hotplug.stats[pin].state = HPD_MARK_DISABLED; in intel_hpd_irq_storm_detect()
170 dev_priv->hotplug.stats[pin].count++; in intel_hpd_irq_storm_detect()
172 dev_priv->hotplug.stats[pin].count); in intel_hpd_irq_storm_detect()
178 static void intel_hpd_irq_storm_disable(struct drm_i915_private *dev_priv) in intel_hpd_irq_storm_disable() argument
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H A Dintel_fifo_underrun.c53 struct drm_i915_private *dev_priv = to_i915(dev); in ivb_can_enable_err_int() local
57 lockdep_assert_held(&dev_priv->irq_lock); in ivb_can_enable_err_int()
59 for_each_pipe(dev_priv, pipe) { in ivb_can_enable_err_int()
60 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); in ivb_can_enable_err_int()
71 struct drm_i915_private *dev_priv = to_i915(dev); in cpt_can_enable_serr_int() local
75 lockdep_assert_held(&dev_priv->irq_lock); in cpt_can_enable_serr_int()
77 for_each_pipe(dev_priv, pipe) { in cpt_can_enable_serr_int()
78 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); in cpt_can_enable_serr_int()
89 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_check_fifo_underruns() local
93 lockdep_assert_held(&dev_priv->irq_lock); in i9xx_check_fifo_underruns()
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H A Di915_drv.h317 #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
595 struct drm_i915_private *dev_priv; member
698 void (*get_cdclk)(struct drm_i915_private *dev_priv,
700 void (*set_cdclk)(struct drm_i915_private *dev_priv,
702 int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
735 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
736 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
1245 struct drm_i915_private *dev_priv; member
1424 void (*sync_hw)(struct drm_i915_private *dev_priv,
1431 void (*enable)(struct drm_i915_private *dev_priv,
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H A Dintel_uc.c31 static int __intel_uc_reset_hw(struct drm_i915_private *dev_priv) in __intel_uc_reset_hw() argument
36 ret = intel_guc_reset(dev_priv); in __intel_uc_reset_hw()
50 void intel_uc_sanitize_options(struct drm_i915_private *dev_priv) in intel_uc_sanitize_options() argument
52 if (!HAS_GUC(dev_priv)) { in intel_uc_sanitize_options()
64 i915_modparams.enable_guc_loading = HAS_GUC_UCODE(dev_priv); in intel_uc_sanitize_options()
68 if (HAS_HUC_UCODE(dev_priv)) in intel_uc_sanitize_options()
69 intel_huc_select_fw(&dev_priv->huc); in intel_uc_sanitize_options()
71 if (intel_guc_fw_select(&dev_priv->guc)) in intel_uc_sanitize_options()
81 i915_modparams.enable_guc_submission = HAS_GUC_SCHED(dev_priv); in intel_uc_sanitize_options()
84 void intel_uc_init_early(struct drm_i915_private *dev_priv) in intel_uc_init_early() argument
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H A Dintel_bios.c204 parse_lfp_panel_data(struct drm_i915_private *dev_priv, in parse_lfp_panel_data() argument
221 dev_priv->vbt.lvds_dither = lvds_options->pixel_dither; in parse_lfp_panel_data()
223 ret = intel_opregion_get_panel_type(dev_priv); in parse_lfp_panel_data()
238 dev_priv->vbt.panel_type = panel_type; in parse_lfp_panel_data()
249 dev_priv->vbt.drrs_type = STATIC_DRRS_SUPPORT; in parse_lfp_panel_data()
253 dev_priv->vbt.drrs_type = SEAMLESS_DRRS_SUPPORT; in parse_lfp_panel_data()
257 dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED; in parse_lfp_panel_data()
270 dev_priv->vbt.lvds_vbt = 1; in parse_lfp_panel_data()
282 dev_priv->vbt.lfp_lvds_vbt_mode = panel_fixed_mode; in parse_lfp_panel_data()
294 dev_priv->vbt.bios_lvds_val = fp_timing->lvds_reg_val; in parse_lfp_panel_data()
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H A Dintel_i2c.c79 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, in get_gmbus_pin() argument
82 if (HAS_PCH_CNP(dev_priv)) in get_gmbus_pin()
84 else if (IS_GEN9_LP(dev_priv)) in get_gmbus_pin()
86 else if (IS_GEN9_BC(dev_priv)) in get_gmbus_pin()
88 else if (IS_BROADWELL(dev_priv)) in get_gmbus_pin()
94 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, in intel_gmbus_is_valid_pin() argument
99 if (HAS_PCH_CNP(dev_priv)) in intel_gmbus_is_valid_pin()
101 else if (IS_GEN9_LP(dev_priv)) in intel_gmbus_is_valid_pin()
103 else if (IS_GEN9_BC(dev_priv)) in intel_gmbus_is_valid_pin()
105 else if (IS_BROADWELL(dev_priv)) in intel_gmbus_is_valid_pin()
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H A Dintel_pm.c58 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) in gen9_init_clock_gating() argument
60 if (HAS_LLC(dev_priv)) { in gen9_init_clock_gating()
94 if (IS_SKYLAKE(dev_priv)) { in gen9_init_clock_gating()
101 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) in bxt_init_clock_gating() argument
103 gen9_init_clock_gating(dev_priv); in bxt_init_clock_gating()
124 static void glk_init_clock_gating(struct drm_i915_private *dev_priv) in glk_init_clock_gating() argument
126 gen9_init_clock_gating(dev_priv); in glk_init_clock_gating()
137 if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1)) { in glk_init_clock_gating()
147 static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv) in i915_pineview_get_mem_freq() argument
155 dev_priv->fsb_freq = 533; /* 133*4 */ in i915_pineview_get_mem_freq()
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H A Di915_gem_shrinker.c38 static bool shrinker_lock(struct drm_i915_private *dev_priv, bool *unlock) in shrinker_lock() argument
40 switch (mutex_trylock_recursive(&dev_priv->drm.struct_mutex)) { in shrinker_lock()
50 if (mutex_trylock(&dev_priv->drm.struct_mutex)) { in shrinker_lock()
66 static void shrinker_unlock(struct drm_i915_private *dev_priv, bool unlock) in shrinker_unlock() argument
71 mutex_unlock(&dev_priv->drm.struct_mutex); in shrinker_unlock()
145 i915_gem_shrink(struct drm_i915_private *dev_priv, in i915_gem_shrink() argument
154 { &dev_priv->mm.unbound_list, I915_SHRINK_UNBOUND }, in i915_gem_shrink()
155 { &dev_priv->mm.bound_list, I915_SHRINK_BOUND }, in i915_gem_shrink()
162 if (!shrinker_lock(dev_priv, &unlock)) in i915_gem_shrink()
175 i915_gem_wait_for_idle(dev_priv, I915_WAIT_LOCKED); in i915_gem_shrink()
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H A Dintel_frontbuffer.c73 struct drm_i915_private *dev_priv = to_i915(obj->base.dev); in __intel_fb_obj_invalidate() local
76 lockmgr(&dev_priv->fb_tracking.lock, LK_EXCLUSIVE); in __intel_fb_obj_invalidate()
77 dev_priv->fb_tracking.busy_bits |= frontbuffer_bits; in __intel_fb_obj_invalidate()
78 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits; in __intel_fb_obj_invalidate()
79 lockmgr(&dev_priv->fb_tracking.lock, LK_RELEASE); in __intel_fb_obj_invalidate()
82 intel_psr_invalidate(dev_priv, frontbuffer_bits); in __intel_fb_obj_invalidate()
83 intel_edp_drrs_invalidate(dev_priv, frontbuffer_bits); in __intel_fb_obj_invalidate()
84 intel_fbc_invalidate(dev_priv, frontbuffer_bits, origin); in __intel_fb_obj_invalidate()
99 static void intel_frontbuffer_flush(struct drm_i915_private *dev_priv, in intel_frontbuffer_flush() argument
104 lockmgr(&dev_priv->fb_tracking.lock, LK_EXCLUSIVE); in intel_frontbuffer_flush()
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H A Di915_sysfs.c43 static u32 calc_residency(struct drm_i915_private *dev_priv,
46 return intel_rc6_residency(dev_priv, reg);
58 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
59 u32 rc6_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6);
66 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
67 u32 rc6p_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6p);
74 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
75 u32 rc6pp_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6pp);
82 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
83 u32 rc6_residency = calc_residency(dev_priv, VLV_GT_MEDIA_RC6);
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H A Dintel_csr.c188 intel_get_stepping_info(struct drm_i915_private *dev_priv) in intel_get_stepping_info() argument
193 if (IS_SKYLAKE(dev_priv)) { in intel_get_stepping_info()
196 } else if (IS_BROXTON(dev_priv)) { in intel_get_stepping_info()
203 if (INTEL_REVID(dev_priv) < size) in intel_get_stepping_info()
204 return si + INTEL_REVID(dev_priv); in intel_get_stepping_info()
209 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) in gen9_set_dc_state_debugmask() argument
215 if (IS_GEN9_LP(dev_priv)) in gen9_set_dc_state_debugmask()
235 void intel_csr_load_program(struct drm_i915_private *dev_priv) in intel_csr_load_program() argument
237 u32 *payload = dev_priv->csr.dmc_payload; in intel_csr_load_program()
240 if (!HAS_CSR(dev_priv)) { in intel_csr_load_program()
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H A Dintel_dpio_phy.c212 bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count) in bxt_get_phy_list() argument
214 if (IS_GEMINILAKE(dev_priv)) { in bxt_get_phy_list()
224 bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy) in bxt_get_phy_info() argument
228 bxt_get_phy_list(dev_priv, &count); in bxt_get_phy_info()
233 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, in bxt_port_to_phy_channel() argument
239 phys = bxt_get_phy_list(dev_priv, &count); in bxt_port_to_phy_channel()
263 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv, in bxt_ddi_phy_set_signal_level() argument
271 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); in bxt_ddi_phy_set_signal_level()
306 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, in bxt_ddi_phy_is_enabled() argument
311 phy_info = bxt_get_phy_info(dev_priv, phy); in bxt_ddi_phy_is_enabled()
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H A Dintel_sideband.c42 static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn, in vlv_sideband_rw() argument
52 WARN_ON(!mutex_is_locked(&dev_priv->sb_lock)); in vlv_sideband_rw()
54 if (intel_wait_for_register(dev_priv, in vlv_sideband_rw()
66 if (intel_wait_for_register(dev_priv, in vlv_sideband_rw()
80 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr) in vlv_punit_read() argument
84 WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock)); in vlv_punit_read()
86 mutex_lock(&dev_priv->sb_lock); in vlv_punit_read()
87 vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT, in vlv_punit_read()
89 mutex_unlock(&dev_priv->sb_lock); in vlv_punit_read()
94 int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val) in vlv_punit_write() argument
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H A Dintel_lpe_audio.c72 #define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->lpe_audio.platdev != NULL) argument
76 lpe_audio_platdev_create(struct drm_i915_private *dev_priv)
79 struct drm_device *dev = &dev_priv->drm;
95 rsc[0].start = rsc[0].end = dev_priv->lpe_audio.irq;
115 pdata->num_pipes = INTEL_INFO(dev_priv)->num_pipes;
116 pdata->num_ports = IS_CHERRYVIEW(dev_priv) ? 3 : 2; /* B,C,D or B,C */
147 static void lpe_audio_platdev_destroy(struct drm_i915_private *dev_priv)
157 platform_device_unregister(dev_priv->lpe_audio.platdev);
174 static int lpe_audio_irq_init(struct drm_i915_private *dev_priv)
176 int irq = dev_priv->lpe_audio.irq;
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H A Di915_gem_stolen.c48 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, in i915_gem_stolen_insert_node_in_range() argument
54 if (!drm_mm_initialized(&dev_priv->mm.stolen)) in i915_gem_stolen_insert_node_in_range()
57 mutex_lock(&dev_priv->mm.stolen_lock); in i915_gem_stolen_insert_node_in_range()
58 ret = drm_mm_insert_node_in_range(&dev_priv->mm.stolen, node, in i915_gem_stolen_insert_node_in_range()
61 mutex_unlock(&dev_priv->mm.stolen_lock); in i915_gem_stolen_insert_node_in_range()
66 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv, in i915_gem_stolen_insert_node() argument
70 return i915_gem_stolen_insert_node_in_range(dev_priv, node, size, in i915_gem_stolen_insert_node()
74 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, in i915_gem_stolen_remove_node() argument
77 mutex_lock(&dev_priv->mm.stolen_lock); in i915_gem_stolen_remove_node()
79 mutex_unlock(&dev_priv->mm.stolen_lock); in i915_gem_stolen_remove_node()
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H A Dintel_drv.h1124 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe) in intel_get_crtc_for_pipe() argument
1126 return dev_priv->pipe_to_crtc_mapping[pipe]; in intel_get_crtc_for_pipe()
1130 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane) in intel_get_crtc_for_plane() argument
1132 return dev_priv->plane_to_crtc_mapping[plane]; in intel_get_crtc_for_plane()
1217 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1219 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1222 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1224 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1226 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1227 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
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