Lines Matching refs:dev_priv
52 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
56 lookup_power_well(struct drm_i915_private *dev_priv,
139 static void intel_power_well_enable(struct drm_i915_private *dev_priv, in intel_power_well_enable() argument
143 power_well->ops->enable(dev_priv, power_well); in intel_power_well_enable()
147 static void intel_power_well_disable(struct drm_i915_private *dev_priv, in intel_power_well_disable() argument
152 power_well->ops->disable(dev_priv, power_well); in intel_power_well_disable()
155 static void intel_power_well_get(struct drm_i915_private *dev_priv, in intel_power_well_get() argument
159 intel_power_well_enable(dev_priv, power_well); in intel_power_well_get()
162 static void intel_power_well_put(struct drm_i915_private *dev_priv, in intel_power_well_put() argument
169 intel_power_well_disable(dev_priv, power_well); in intel_power_well_put()
184 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, in __intel_display_power_is_enabled() argument
190 if (dev_priv->runtime_pm.suspended) in __intel_display_power_is_enabled()
195 for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain)) { in __intel_display_power_is_enabled()
225 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, in intel_display_power_is_enabled() argument
231 power_domains = &dev_priv->power_domains; in intel_display_power_is_enabled()
234 ret = __intel_display_power_is_enabled(dev_priv, domain); in intel_display_power_is_enabled()
250 void intel_display_set_init_power(struct drm_i915_private *dev_priv, in intel_display_set_init_power() argument
253 if (dev_priv->power_domains.init_power_on == enable) in intel_display_set_init_power()
257 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); in intel_display_set_init_power()
259 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); in intel_display_set_init_power()
261 dev_priv->power_domains.init_power_on = enable; in intel_display_set_init_power()
270 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv, in hsw_power_well_post_enable() argument
273 struct pci_dev *pdev = dev_priv->drm.pdev; in hsw_power_well_post_enable()
292 gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask); in hsw_power_well_post_enable()
295 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv, in hsw_power_well_pre_disable() argument
299 gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask); in hsw_power_well_pre_disable()
303 static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, in hsw_wait_for_power_well_enable() argument
309 WARN_ON(intel_wait_for_register(dev_priv, in hsw_wait_for_power_well_enable()
316 static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv, in hsw_power_well_requesters() argument
330 static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv, in hsw_wait_for_power_well_disable() argument
348 (reqs = hsw_power_well_requesters(dev_priv, id)), 1); in hsw_wait_for_power_well_disable()
357 static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv, in gen9_wait_for_power_well_fuses() argument
361 WARN_ON(intel_wait_for_register(dev_priv, SKL_FUSE_STATUS, in gen9_wait_for_power_well_fuses()
366 static void hsw_power_well_enable(struct drm_i915_private *dev_priv, in hsw_power_well_enable() argument
384 gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0); in hsw_power_well_enable()
389 hsw_wait_for_power_well_enable(dev_priv, power_well); in hsw_power_well_enable()
392 gen9_wait_for_power_well_fuses(dev_priv, pg); in hsw_power_well_enable()
394 hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask, in hsw_power_well_enable()
398 static void hsw_power_well_disable(struct drm_i915_private *dev_priv, in hsw_power_well_disable() argument
404 hsw_power_well_pre_disable(dev_priv, power_well->hsw.irq_pipe_mask); in hsw_power_well_disable()
409 hsw_wait_for_power_well_disable(dev_priv, power_well); in hsw_power_well_disable()
417 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, in hsw_power_well_enabled() argument
426 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) in assert_can_enable_dc9() argument
437 WARN_ONCE(intel_irqs_enabled(dev_priv), in assert_can_enable_dc9()
449 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) in assert_can_disable_dc9() argument
451 WARN_ONCE(intel_irqs_enabled(dev_priv), in assert_can_disable_dc9()
465 static void gen9_write_dc_state(struct drm_i915_private *dev_priv, in gen9_write_dc_state() argument
502 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) in gen9_dc_mask() argument
507 if (IS_GEN9_LP(dev_priv)) in gen9_dc_mask()
515 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv) in gen9_sanitize_dc_state() argument
519 val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv); in gen9_sanitize_dc_state()
522 dev_priv->csr.dc_state, val); in gen9_sanitize_dc_state()
523 dev_priv->csr.dc_state = val; in gen9_sanitize_dc_state()
526 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state) in gen9_set_dc_state() argument
531 if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask)) in gen9_set_dc_state()
532 state &= dev_priv->csr.allowed_dc_mask; in gen9_set_dc_state()
535 mask = gen9_dc_mask(dev_priv); in gen9_set_dc_state()
540 if ((val & mask) != dev_priv->csr.dc_state) in gen9_set_dc_state()
542 dev_priv->csr.dc_state, val & mask); in gen9_set_dc_state()
547 gen9_write_dc_state(dev_priv, val); in gen9_set_dc_state()
549 dev_priv->csr.dc_state = val & mask; in gen9_set_dc_state()
552 void bxt_enable_dc9(struct drm_i915_private *dev_priv) in bxt_enable_dc9() argument
554 assert_can_enable_dc9(dev_priv); in bxt_enable_dc9()
558 intel_power_sequencer_reset(dev_priv); in bxt_enable_dc9()
559 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9); in bxt_enable_dc9()
562 void bxt_disable_dc9(struct drm_i915_private *dev_priv) in bxt_disable_dc9() argument
564 assert_can_disable_dc9(dev_priv); in bxt_disable_dc9()
568 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); in bxt_disable_dc9()
570 intel_pps_unlock_regs_wa(dev_priv); in bxt_disable_dc9()
573 static void assert_csr_loaded(struct drm_i915_private *dev_priv) in assert_csr_loaded() argument
581 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) in assert_can_enable_dc5() argument
583 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, in assert_can_enable_dc5()
590 assert_rpm_wakelock_held(dev_priv); in assert_can_enable_dc5()
592 assert_csr_loaded(dev_priv); in assert_can_enable_dc5()
595 void gen9_enable_dc5(struct drm_i915_private *dev_priv) in gen9_enable_dc5() argument
597 assert_can_enable_dc5(dev_priv); in gen9_enable_dc5()
602 if (IS_GEN9_BC(dev_priv)) in gen9_enable_dc5()
606 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); in gen9_enable_dc5()
609 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) in assert_can_enable_dc6() argument
616 assert_csr_loaded(dev_priv); in assert_can_enable_dc6()
619 void skl_enable_dc6(struct drm_i915_private *dev_priv) in skl_enable_dc6() argument
621 assert_can_enable_dc6(dev_priv); in skl_enable_dc6()
625 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); in skl_enable_dc6()
629 void skl_disable_dc6(struct drm_i915_private *dev_priv) in skl_disable_dc6() argument
634 if (IS_GEN9_BC(dev_priv)) in skl_disable_dc6()
638 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); in skl_disable_dc6()
641 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, in hsw_power_well_sync_hw() argument
658 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, in bxt_dpio_cmn_power_well_enable() argument
661 bxt_ddi_phy_init(dev_priv, power_well->bxt.phy); in bxt_dpio_cmn_power_well_enable()
664 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, in bxt_dpio_cmn_power_well_disable() argument
667 bxt_ddi_phy_uninit(dev_priv, power_well->bxt.phy); in bxt_dpio_cmn_power_well_disable()
670 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv, in bxt_dpio_cmn_power_well_enabled() argument
673 return bxt_ddi_phy_is_enabled(dev_priv, power_well->bxt.phy); in bxt_dpio_cmn_power_well_enabled()
676 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv) in bxt_verify_ddi_phy_power_wells() argument
680 power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A); in bxt_verify_ddi_phy_power_wells()
682 bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); in bxt_verify_ddi_phy_power_wells()
684 power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC); in bxt_verify_ddi_phy_power_wells()
686 bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); in bxt_verify_ddi_phy_power_wells()
688 if (IS_GEMINILAKE(dev_priv)) { in bxt_verify_ddi_phy_power_wells()
689 power_well = lookup_power_well(dev_priv, GLK_DPIO_CMN_C); in bxt_verify_ddi_phy_power_wells()
691 bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); in bxt_verify_ddi_phy_power_wells()
695 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, in gen9_dc_off_power_well_enabled() argument
701 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) in gen9_assert_dbuf_enabled() argument
710 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, in gen9_dc_off_power_well_enable() argument
715 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); in gen9_dc_off_power_well_enable()
717 dev_priv->display.get_cdclk(dev_priv, &cdclk_state); in gen9_dc_off_power_well_enable()
718 WARN_ON(!intel_cdclk_state_compare(&dev_priv->cdclk.hw, &cdclk_state)); in gen9_dc_off_power_well_enable()
720 gen9_assert_dbuf_enabled(dev_priv); in gen9_dc_off_power_well_enable()
722 if (IS_GEN9_LP(dev_priv)) in gen9_dc_off_power_well_enable()
723 bxt_verify_ddi_phy_power_wells(dev_priv); in gen9_dc_off_power_well_enable()
726 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, in gen9_dc_off_power_well_disable() argument
729 if (!dev_priv->csr.dmc_payload) in gen9_dc_off_power_well_disable()
732 if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6) in gen9_dc_off_power_well_disable()
733 skl_enable_dc6(dev_priv); in gen9_dc_off_power_well_disable()
734 else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5) in gen9_dc_off_power_well_disable()
735 gen9_enable_dc5(dev_priv); in gen9_dc_off_power_well_disable()
738 static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv, in i9xx_power_well_sync_hw_noop() argument
743 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, in i9xx_always_on_power_well_noop() argument
748 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, in i9xx_always_on_power_well_enabled() argument
754 static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv, in i830_pipes_power_well_enable() argument
758 i830_enable_pipe(dev_priv, PIPE_A); in i830_pipes_power_well_enable()
760 i830_enable_pipe(dev_priv, PIPE_B); in i830_pipes_power_well_enable()
763 static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv, in i830_pipes_power_well_disable() argument
766 i830_disable_pipe(dev_priv, PIPE_B); in i830_pipes_power_well_disable()
767 i830_disable_pipe(dev_priv, PIPE_A); in i830_pipes_power_well_disable()
770 static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv, in i830_pipes_power_well_enabled() argument
777 static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv, in i830_pipes_power_well_sync_hw() argument
781 i830_pipes_power_well_enable(dev_priv, power_well); in i830_pipes_power_well_sync_hw()
783 i830_pipes_power_well_disable(dev_priv, power_well); in i830_pipes_power_well_sync_hw()
786 static void vlv_set_power_well(struct drm_i915_private *dev_priv, in vlv_set_power_well() argument
798 mutex_lock(&dev_priv->pcu_lock); in vlv_set_power_well()
801 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) in vlv_set_power_well()
806 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); in vlv_set_power_well()
809 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); in vlv_set_power_well()
814 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); in vlv_set_power_well()
819 mutex_unlock(&dev_priv->pcu_lock); in vlv_set_power_well()
822 static void vlv_power_well_enable(struct drm_i915_private *dev_priv, in vlv_power_well_enable() argument
825 vlv_set_power_well(dev_priv, power_well, true); in vlv_power_well_enable()
828 static void vlv_power_well_disable(struct drm_i915_private *dev_priv, in vlv_power_well_disable() argument
831 vlv_set_power_well(dev_priv, power_well, false); in vlv_power_well_disable()
834 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, in vlv_power_well_enabled() argument
846 mutex_lock(&dev_priv->pcu_lock); in vlv_power_well_enabled()
848 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; in vlv_power_well_enabled()
862 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; in vlv_power_well_enabled()
865 mutex_unlock(&dev_priv->pcu_lock); in vlv_power_well_enabled()
870 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) in vlv_init_display_clock_gating() argument
891 WARN_ON(dev_priv->rawclk_freq == 0); in vlv_init_display_clock_gating()
894 DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000)); in vlv_init_display_clock_gating()
897 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) in vlv_display_power_well_init() argument
910 for_each_pipe(dev_priv, pipe) { in vlv_display_power_well_init()
920 vlv_init_display_clock_gating(dev_priv); in vlv_display_power_well_init()
922 spin_lock_irq(&dev_priv->irq_lock); in vlv_display_power_well_init()
923 valleyview_enable_display_irqs(dev_priv); in vlv_display_power_well_init()
924 spin_unlock_irq(&dev_priv->irq_lock); in vlv_display_power_well_init()
930 if (dev_priv->power_domains.initializing) in vlv_display_power_well_init()
933 intel_hpd_init(dev_priv); in vlv_display_power_well_init()
936 for_each_intel_encoder(&dev_priv->drm, encoder) { in vlv_display_power_well_init()
941 i915_redisable_vga_power_on(dev_priv); in vlv_display_power_well_init()
943 intel_pps_unlock_regs_wa(dev_priv); in vlv_display_power_well_init()
946 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) in vlv_display_power_well_deinit() argument
948 spin_lock_irq(&dev_priv->irq_lock); in vlv_display_power_well_deinit()
949 valleyview_disable_display_irqs(dev_priv); in vlv_display_power_well_deinit()
950 spin_unlock_irq(&dev_priv->irq_lock); in vlv_display_power_well_deinit()
953 synchronize_irq(dev_priv->drm.irq); in vlv_display_power_well_deinit()
955 intel_power_sequencer_reset(dev_priv); in vlv_display_power_well_deinit()
958 if (!dev_priv->drm.dev->power.is_suspended) in vlv_display_power_well_deinit()
959 intel_hpd_poll_init(dev_priv); in vlv_display_power_well_deinit()
962 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, in vlv_display_power_well_enable() argument
967 vlv_set_power_well(dev_priv, power_well, true); in vlv_display_power_well_enable()
969 vlv_display_power_well_init(dev_priv); in vlv_display_power_well_enable()
972 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, in vlv_display_power_well_disable() argument
977 vlv_display_power_well_deinit(dev_priv); in vlv_display_power_well_disable()
979 vlv_set_power_well(dev_priv, power_well, false); in vlv_display_power_well_disable()
982 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, in vlv_dpio_cmn_power_well_enable() argument
990 vlv_set_power_well(dev_priv, power_well, true); in vlv_dpio_cmn_power_well_enable()
1006 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, in vlv_dpio_cmn_power_well_disable() argument
1013 for_each_pipe(dev_priv, pipe) in vlv_dpio_cmn_power_well_disable()
1014 assert_pll_disabled(dev_priv, pipe); in vlv_dpio_cmn_power_well_disable()
1019 vlv_set_power_well(dev_priv, power_well, false); in vlv_dpio_cmn_power_well_disable()
1025 lookup_power_well(struct drm_i915_private *dev_priv, in lookup_power_well() argument
1028 struct i915_power_domains *power_domains = &dev_priv->power_domains; in lookup_power_well()
1044 static void assert_chv_phy_status(struct drm_i915_private *dev_priv) in assert_chv_phy_status() argument
1047 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); in assert_chv_phy_status()
1049 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); in assert_chv_phy_status()
1050 u32 phy_control = dev_priv->chv_phy_control; in assert_chv_phy_status()
1061 if (!dev_priv->chv_phy_assert[DPIO_PHY0]) in assert_chv_phy_status()
1069 if (!dev_priv->chv_phy_assert[DPIO_PHY1]) in assert_chv_phy_status()
1074 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { in assert_chv_phy_status()
1115 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { in assert_chv_phy_status()
1140 if (intel_wait_for_register(dev_priv, in assert_chv_phy_status()
1147 phy_status, dev_priv->chv_phy_control); in assert_chv_phy_status()
1152 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, in chv_dpio_cmn_power_well_enable() argument
1172 vlv_set_power_well(dev_priv, power_well, true); in chv_dpio_cmn_power_well_enable()
1175 if (intel_wait_for_register(dev_priv, in chv_dpio_cmn_power_well_enable()
1182 mutex_lock(&dev_priv->sb_lock); in chv_dpio_cmn_power_well_enable()
1185 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); in chv_dpio_cmn_power_well_enable()
1188 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp); in chv_dpio_cmn_power_well_enable()
1191 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); in chv_dpio_cmn_power_well_enable()
1193 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp); in chv_dpio_cmn_power_well_enable()
1200 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); in chv_dpio_cmn_power_well_enable()
1202 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp); in chv_dpio_cmn_power_well_enable()
1205 mutex_unlock(&dev_priv->sb_lock); in chv_dpio_cmn_power_well_enable()
1207 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); in chv_dpio_cmn_power_well_enable()
1208 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); in chv_dpio_cmn_power_well_enable()
1211 phy, dev_priv->chv_phy_control); in chv_dpio_cmn_power_well_enable()
1213 assert_chv_phy_status(dev_priv); in chv_dpio_cmn_power_well_enable()
1216 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, in chv_dpio_cmn_power_well_disable() argument
1226 assert_pll_disabled(dev_priv, PIPE_A); in chv_dpio_cmn_power_well_disable()
1227 assert_pll_disabled(dev_priv, PIPE_B); in chv_dpio_cmn_power_well_disable()
1230 assert_pll_disabled(dev_priv, PIPE_C); in chv_dpio_cmn_power_well_disable()
1233 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); in chv_dpio_cmn_power_well_disable()
1234 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); in chv_dpio_cmn_power_well_disable()
1236 vlv_set_power_well(dev_priv, power_well, false); in chv_dpio_cmn_power_well_disable()
1239 phy, dev_priv->chv_phy_control); in chv_dpio_cmn_power_well_disable()
1242 dev_priv->chv_phy_assert[phy] = true; in chv_dpio_cmn_power_well_disable()
1244 assert_chv_phy_status(dev_priv); in chv_dpio_cmn_power_well_disable()
1247 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy, in assert_chv_phy_powergate() argument
1260 if (!dev_priv->chv_phy_assert[phy]) in assert_chv_phy_powergate()
1268 mutex_lock(&dev_priv->sb_lock); in assert_chv_phy_powergate()
1269 val = vlv_dpio_read(dev_priv, pipe, reg); in assert_chv_phy_powergate()
1270 mutex_unlock(&dev_priv->sb_lock); in assert_chv_phy_powergate()
1309 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, in chv_phy_powergate_ch() argument
1312 struct i915_power_domains *power_domains = &dev_priv->power_domains; in chv_phy_powergate_ch()
1317 was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); in chv_phy_powergate_ch()
1323 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); in chv_phy_powergate_ch()
1325 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); in chv_phy_powergate_ch()
1327 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); in chv_phy_powergate_ch()
1330 phy, ch, dev_priv->chv_phy_control); in chv_phy_powergate_ch()
1332 assert_chv_phy_status(dev_priv); in chv_phy_powergate_ch()
1343 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_phy_powergate_lanes() local
1344 struct i915_power_domains *power_domains = &dev_priv->power_domains; in chv_phy_powergate_lanes()
1350 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); in chv_phy_powergate_lanes()
1351 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); in chv_phy_powergate_lanes()
1354 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); in chv_phy_powergate_lanes()
1356 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); in chv_phy_powergate_lanes()
1358 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); in chv_phy_powergate_lanes()
1361 phy, ch, mask, dev_priv->chv_phy_control); in chv_phy_powergate_lanes()
1363 assert_chv_phy_status(dev_priv); in chv_phy_powergate_lanes()
1365 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask); in chv_phy_powergate_lanes()
1370 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, in chv_pipe_power_well_enabled() argument
1377 mutex_lock(&dev_priv->pcu_lock); in chv_pipe_power_well_enabled()
1379 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); in chv_pipe_power_well_enabled()
1391 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); in chv_pipe_power_well_enabled()
1394 mutex_unlock(&dev_priv->pcu_lock); in chv_pipe_power_well_enabled()
1399 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, in chv_set_pipe_power_well() argument
1409 mutex_lock(&dev_priv->pcu_lock); in chv_set_pipe_power_well()
1412 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) in chv_set_pipe_power_well()
1417 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); in chv_set_pipe_power_well()
1420 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); in chv_set_pipe_power_well()
1425 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); in chv_set_pipe_power_well()
1430 mutex_unlock(&dev_priv->pcu_lock); in chv_set_pipe_power_well()
1433 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, in chv_pipe_power_well_enable() argument
1438 chv_set_pipe_power_well(dev_priv, power_well, true); in chv_pipe_power_well_enable()
1440 vlv_display_power_well_init(dev_priv); in chv_pipe_power_well_enable()
1443 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, in chv_pipe_power_well_disable() argument
1448 vlv_display_power_well_deinit(dev_priv); in chv_pipe_power_well_disable()
1450 chv_set_pipe_power_well(dev_priv, power_well, false); in chv_pipe_power_well_disable()
1454 __intel_display_power_get_domain(struct drm_i915_private *dev_priv, in __intel_display_power_get_domain() argument
1457 struct i915_power_domains *power_domains = &dev_priv->power_domains; in __intel_display_power_get_domain()
1460 for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain)) in __intel_display_power_get_domain()
1461 intel_power_well_get(dev_priv, power_well); in __intel_display_power_get_domain()
1478 void intel_display_power_get(struct drm_i915_private *dev_priv, in intel_display_power_get() argument
1481 struct i915_power_domains *power_domains = &dev_priv->power_domains; in intel_display_power_get()
1483 intel_runtime_pm_get(dev_priv); in intel_display_power_get()
1487 __intel_display_power_get_domain(dev_priv, domain); in intel_display_power_get()
1504 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, in intel_display_power_get_if_enabled() argument
1507 struct i915_power_domains *power_domains = &dev_priv->power_domains; in intel_display_power_get_if_enabled()
1510 if (!intel_runtime_pm_get_if_in_use(dev_priv)) in intel_display_power_get_if_enabled()
1515 if (__intel_display_power_is_enabled(dev_priv, domain)) { in intel_display_power_get_if_enabled()
1516 __intel_display_power_get_domain(dev_priv, domain); in intel_display_power_get_if_enabled()
1525 intel_runtime_pm_put(dev_priv); in intel_display_power_get_if_enabled()
1539 void intel_display_power_put(struct drm_i915_private *dev_priv, in intel_display_power_put() argument
1545 power_domains = &dev_priv->power_domains; in intel_display_power_put()
1554 for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain)) in intel_display_power_put()
1555 intel_power_well_put(dev_priv, power_well); in intel_display_power_put()
1559 intel_runtime_pm_put(dev_priv); in intel_display_power_put()
2076 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, in intel_display_power_well_is_enabled() argument
2082 power_well = lookup_power_well(dev_priv, power_well_id); in intel_display_power_well_is_enabled()
2083 ret = power_well->ops->is_enabled(dev_priv, power_well); in intel_display_power_well_is_enabled()
2396 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv, in sanitize_disable_power_well_option() argument
2405 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv, in get_allowed_dc_mask() argument
2412 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { in get_allowed_dc_mask()
2415 } else if (IS_GEN9_LP(dev_priv)) { in get_allowed_dc_mask()
2454 static void assert_power_well_ids_unique(struct drm_i915_private *dev_priv) in assert_power_well_ids_unique() argument
2456 struct i915_power_domains *power_domains = &dev_priv->power_domains; in assert_power_well_ids_unique()
2482 int intel_power_domains_init(struct drm_i915_private *dev_priv) in intel_power_domains_init() argument
2484 struct i915_power_domains *power_domains = &dev_priv->power_domains; in intel_power_domains_init()
2487 sanitize_disable_power_well_option(dev_priv, in intel_power_domains_init()
2489 dev_priv->csr.allowed_dc_mask = in intel_power_domains_init()
2490 get_allowed_dc_mask(dev_priv, i915_modparams.enable_dc); in intel_power_domains_init()
2500 if (IS_HASWELL(dev_priv)) { in intel_power_domains_init()
2502 } else if (IS_BROADWELL(dev_priv)) { in intel_power_domains_init()
2504 } else if (IS_GEN9_BC(dev_priv)) { in intel_power_domains_init()
2506 } else if (IS_CANNONLAKE(dev_priv)) { in intel_power_domains_init()
2508 } else if (IS_BROXTON(dev_priv)) { in intel_power_domains_init()
2510 } else if (IS_GEMINILAKE(dev_priv)) { in intel_power_domains_init()
2512 } else if (IS_CHERRYVIEW(dev_priv)) { in intel_power_domains_init()
2514 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_power_domains_init()
2516 } else if (IS_I830(dev_priv)) { in intel_power_domains_init()
2522 assert_power_well_ids_unique(dev_priv); in intel_power_domains_init()
2535 void intel_power_domains_fini(struct drm_i915_private *dev_priv) in intel_power_domains_fini() argument
2538 struct device *kdev = &dev_priv->drm.pdev->dev; in intel_power_domains_fini()
2550 intel_display_set_init_power(dev_priv, true); in intel_power_domains_fini()
2554 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); in intel_power_domains_fini()
2561 if (!HAS_RUNTIME_PM(dev_priv)) in intel_power_domains_fini()
2566 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv) in intel_power_domains_sync_hw() argument
2568 struct i915_power_domains *power_domains = &dev_priv->power_domains; in intel_power_domains_sync_hw()
2572 for_each_power_well(dev_priv, power_well) { in intel_power_domains_sync_hw()
2573 power_well->ops->sync_hw(dev_priv, power_well); in intel_power_domains_sync_hw()
2574 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, in intel_power_domains_sync_hw()
2580 static void gen9_dbuf_enable(struct drm_i915_private *dev_priv) in gen9_dbuf_enable() argument
2591 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) in gen9_dbuf_disable() argument
2602 static void skl_display_core_init(struct drm_i915_private *dev_priv, in skl_display_core_init() argument
2605 struct i915_power_domains *power_domains = &dev_priv->power_domains; in skl_display_core_init()
2609 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); in skl_display_core_init()
2618 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); in skl_display_core_init()
2619 intel_power_well_enable(dev_priv, well); in skl_display_core_init()
2621 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); in skl_display_core_init()
2622 intel_power_well_enable(dev_priv, well); in skl_display_core_init()
2626 skl_init_cdclk(dev_priv); in skl_display_core_init()
2628 gen9_dbuf_enable(dev_priv); in skl_display_core_init()
2630 if (resume && dev_priv->csr.dmc_payload) in skl_display_core_init()
2631 intel_csr_load_program(dev_priv); in skl_display_core_init()
2634 static void skl_display_core_uninit(struct drm_i915_private *dev_priv) in skl_display_core_uninit() argument
2636 struct i915_power_domains *power_domains = &dev_priv->power_domains; in skl_display_core_uninit()
2639 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); in skl_display_core_uninit()
2641 gen9_dbuf_disable(dev_priv); in skl_display_core_uninit()
2643 skl_uninit_cdclk(dev_priv); in skl_display_core_uninit()
2656 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); in skl_display_core_uninit()
2657 intel_power_well_disable(dev_priv, well); in skl_display_core_uninit()
2664 void bxt_display_core_init(struct drm_i915_private *dev_priv, in bxt_display_core_init() argument
2667 struct i915_power_domains *power_domains = &dev_priv->power_domains; in bxt_display_core_init()
2671 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); in bxt_display_core_init()
2686 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); in bxt_display_core_init()
2687 intel_power_well_enable(dev_priv, well); in bxt_display_core_init()
2691 bxt_init_cdclk(dev_priv); in bxt_display_core_init()
2693 gen9_dbuf_enable(dev_priv); in bxt_display_core_init()
2695 if (resume && dev_priv->csr.dmc_payload) in bxt_display_core_init()
2696 intel_csr_load_program(dev_priv); in bxt_display_core_init()
2699 void bxt_display_core_uninit(struct drm_i915_private *dev_priv) in bxt_display_core_uninit() argument
2701 struct i915_power_domains *power_domains = &dev_priv->power_domains; in bxt_display_core_uninit()
2704 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); in bxt_display_core_uninit()
2706 gen9_dbuf_disable(dev_priv); in bxt_display_core_uninit()
2708 bxt_uninit_cdclk(dev_priv); in bxt_display_core_uninit()
2719 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); in bxt_display_core_uninit()
2720 intel_power_well_disable(dev_priv, well); in bxt_display_core_uninit()
2750 static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv) in cnl_set_procmon_ref_values() argument
2785 static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume) in cnl_display_core_init() argument
2787 struct i915_power_domains *power_domains = &dev_priv->power_domains; in cnl_display_core_init()
2791 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); in cnl_display_core_init()
2803 cnl_set_procmon_ref_values(dev_priv); in cnl_display_core_init()
2819 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); in cnl_display_core_init()
2820 intel_power_well_enable(dev_priv, well); in cnl_display_core_init()
2824 cnl_init_cdclk(dev_priv); in cnl_display_core_init()
2827 gen9_dbuf_enable(dev_priv); in cnl_display_core_init()
2829 if (resume && dev_priv->csr.dmc_payload) in cnl_display_core_init()
2830 intel_csr_load_program(dev_priv); in cnl_display_core_init()
2833 static void cnl_display_core_uninit(struct drm_i915_private *dev_priv) in cnl_display_core_uninit() argument
2835 struct i915_power_domains *power_domains = &dev_priv->power_domains; in cnl_display_core_uninit()
2839 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); in cnl_display_core_uninit()
2844 gen9_dbuf_disable(dev_priv); in cnl_display_core_uninit()
2847 cnl_uninit_cdclk(dev_priv); in cnl_display_core_uninit()
2855 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); in cnl_display_core_uninit()
2856 intel_power_well_disable(dev_priv, well); in cnl_display_core_uninit()
2867 static void chv_phy_control_init(struct drm_i915_private *dev_priv) in chv_phy_control_init() argument
2870 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); in chv_phy_control_init()
2872 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); in chv_phy_control_init()
2881 dev_priv->chv_phy_control = in chv_phy_control_init()
2895 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { in chv_phy_control_init()
2903 dev_priv->chv_phy_control |= in chv_phy_control_init()
2906 dev_priv->chv_phy_control |= in chv_phy_control_init()
2913 dev_priv->chv_phy_control |= in chv_phy_control_init()
2916 dev_priv->chv_phy_control |= in chv_phy_control_init()
2919 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); in chv_phy_control_init()
2921 dev_priv->chv_phy_assert[DPIO_PHY0] = false; in chv_phy_control_init()
2923 dev_priv->chv_phy_assert[DPIO_PHY0] = true; in chv_phy_control_init()
2926 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { in chv_phy_control_init()
2935 dev_priv->chv_phy_control |= in chv_phy_control_init()
2938 dev_priv->chv_phy_control |= in chv_phy_control_init()
2941 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); in chv_phy_control_init()
2943 dev_priv->chv_phy_assert[DPIO_PHY1] = false; in chv_phy_control_init()
2945 dev_priv->chv_phy_assert[DPIO_PHY1] = true; in chv_phy_control_init()
2948 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); in chv_phy_control_init()
2951 dev_priv->chv_phy_control); in chv_phy_control_init()
2954 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) in vlv_cmnlane_wa() argument
2957 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); in vlv_cmnlane_wa()
2959 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); in vlv_cmnlane_wa()
2962 if (cmn->ops->is_enabled(dev_priv, cmn) && in vlv_cmnlane_wa()
2963 disp2d->ops->is_enabled(dev_priv, disp2d) && in vlv_cmnlane_wa()
2970 disp2d->ops->enable(dev_priv, disp2d); in vlv_cmnlane_wa()
2979 cmn->ops->disable(dev_priv, cmn); in vlv_cmnlane_wa()
2993 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume) in intel_power_domains_init_hw() argument
2995 struct i915_power_domains *power_domains = &dev_priv->power_domains; in intel_power_domains_init_hw()
2999 if (IS_CANNONLAKE(dev_priv)) { in intel_power_domains_init_hw()
3000 cnl_display_core_init(dev_priv, resume); in intel_power_domains_init_hw()
3001 } else if (IS_GEN9_BC(dev_priv)) { in intel_power_domains_init_hw()
3002 skl_display_core_init(dev_priv, resume); in intel_power_domains_init_hw()
3003 } else if (IS_GEN9_LP(dev_priv)) { in intel_power_domains_init_hw()
3004 bxt_display_core_init(dev_priv, resume); in intel_power_domains_init_hw()
3005 } else if (IS_CHERRYVIEW(dev_priv)) { in intel_power_domains_init_hw()
3007 chv_phy_control_init(dev_priv); in intel_power_domains_init_hw()
3009 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_power_domains_init_hw()
3011 vlv_cmnlane_wa(dev_priv); in intel_power_domains_init_hw()
3016 intel_display_set_init_power(dev_priv, true); in intel_power_domains_init_hw()
3019 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); in intel_power_domains_init_hw()
3020 intel_power_domains_sync_hw(dev_priv); in intel_power_domains_init_hw()
3031 void intel_power_domains_suspend(struct drm_i915_private *dev_priv) in intel_power_domains_suspend() argument
3038 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); in intel_power_domains_suspend()
3040 if (IS_CANNONLAKE(dev_priv)) in intel_power_domains_suspend()
3041 cnl_display_core_uninit(dev_priv); in intel_power_domains_suspend()
3042 else if (IS_GEN9_BC(dev_priv)) in intel_power_domains_suspend()
3043 skl_display_core_uninit(dev_priv); in intel_power_domains_suspend()
3044 else if (IS_GEN9_LP(dev_priv)) in intel_power_domains_suspend()
3045 bxt_display_core_uninit(dev_priv); in intel_power_domains_suspend()
3048 static void intel_power_domains_dump_info(struct drm_i915_private *dev_priv) in intel_power_domains_dump_info() argument
3050 struct i915_power_domains *power_domains = &dev_priv->power_domains; in intel_power_domains_dump_info()
3053 for_each_power_well(dev_priv, power_well) { in intel_power_domains_dump_info()
3076 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv) in intel_power_domains_verify_state() argument
3078 struct i915_power_domains *power_domains = &dev_priv->power_domains; in intel_power_domains_verify_state()
3085 for_each_power_well(dev_priv, power_well) { in intel_power_domains_verify_state()
3098 enabled = power_well->ops->is_enabled(dev_priv, power_well); in intel_power_domains_verify_state()
3120 intel_power_domains_dump_info(dev_priv); in intel_power_domains_verify_state()
3138 void intel_runtime_pm_get(struct drm_i915_private *dev_priv) in intel_runtime_pm_get() argument
3140 struct pci_dev *pdev = dev_priv->drm.pdev; in intel_runtime_pm_get()
3147 atomic_inc(&dev_priv->runtime_pm.wakeref_count); in intel_runtime_pm_get()
3148 assert_rpm_wakelock_held(dev_priv); in intel_runtime_pm_get()
3161 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv) in intel_runtime_pm_get_if_in_use() argument
3164 struct pci_dev *pdev = dev_priv->drm.pdev; in intel_runtime_pm_get_if_in_use()
3182 atomic_inc(&dev_priv->runtime_pm.wakeref_count); in intel_runtime_pm_get_if_in_use()
3183 assert_rpm_wakelock_held(dev_priv); in intel_runtime_pm_get_if_in_use()
3206 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) in intel_runtime_pm_get_noresume() argument
3209 struct pci_dev *pdev = dev_priv->drm.pdev; in intel_runtime_pm_get_noresume()
3213 assert_rpm_wakelock_held(dev_priv); in intel_runtime_pm_get_noresume()
3218 atomic_inc(&dev_priv->runtime_pm.wakeref_count); in intel_runtime_pm_get_noresume()
3229 void intel_runtime_pm_put(struct drm_i915_private *dev_priv) in intel_runtime_pm_put() argument
3231 struct pci_dev *pdev = dev_priv->drm.pdev; in intel_runtime_pm_put()
3234 assert_rpm_wakelock_held(dev_priv); in intel_runtime_pm_put()
3235 atomic_dec(&dev_priv->runtime_pm.wakeref_count); in intel_runtime_pm_put()
3251 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) in intel_runtime_pm_enable() argument
3254 struct pci_dev *pdev = dev_priv->drm.pdev; in intel_runtime_pm_enable()
3266 if (!HAS_RUNTIME_PM(dev_priv)) { in intel_runtime_pm_enable()