| /freebsd-src/contrib/llvm-project/llvm/lib/TargetParser/ |
| H A D | X86TargetParser.cpp | 103 // Intel Skylake processors.
118 // Intel 10nm processors.
142 // Intel Atom processors.
179 // K7 and K8 architecture processors.
191 // Bobcat architecture processors.
201 // AMD Bulldozer architecture processors.
217 // AMD Zen architecture processors.
254 constexpr ProcInfo Processors[] = {
258 // i386-generation processors.
260 // i486-generation processors
250 constexpr ProcInfo Processors[] = { global() variable
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64.td | 52 // AArch64 Processors supported.
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARM.td | |
| /freebsd-src/share/man/man4/ |
| H A D | amdtemp.4 | 54 Family 0Fh, 10h, 11h, 12h, 14h, 15h, 16h, and 17h processors.
56 For Family 0Fh processors, the
65 For Family 10h, 11h, 12h, 14h, 15h, 16h, and 17h processors, the driver reports
97 For Family 10h and later processors,
108 .%T BIOS and Kernel Developer's Guide (BKDG) for AMD Processors
|
| /freebsd-src/lib/libpmc/pmu-events/arch/x86/goldmont/ |
| H A D | frontend.json | 43 … "References per ICache line. This event counts differently than Intel processors based on Silverm…
48 …h target is to a new line.\r\nThis event counts differently than Intel processors based on Silverm…
53 …vailable in the ICache (hit). This event counts differently than Intel processors based on Silverm…
58 … cache line is in the ICache. This event counts differently than Intel processors based on Silverm…
63 …ailable in the ICache (miss). This event counts differently than Intel processors based on Silverm…
68 …he line is not in the ICache. This event counts differently than Intel processors based on Silverm…
|
| /freebsd-src/lib/libc/softfloat/ |
| H A D | softfloat-source.txt | 63 processors/*.h
104 processors
118 processors - Target-specific header files that are not specific to
167 processors/*.h
169 The target-specific `processors' header file defines integer types
202 in `softfloat.h' do not use any of the types defined by the `processors'
204 `processors' header file in order to use SoftFloat. Nevertheless, the
206 expects. For example, if `int32' is defined as `int' in the `processors'
269 processors/*.h
274 Note in particular that `softfloat.c' does not include the `processors'
[all …]
|
| /freebsd-src/sys/contrib/libsodium/dist-build/ |
| H A D | ios.sh | 49 PROCESSORS=${NPROCESSORS:-3}
51 make -j${PROCESSORS} install || exit 1
64 make -j${PROCESSORS} install || exit 1
82 make -j${PROCESSORS} install || exit 1
95 make -j${PROCESSORS} install || exit 1
108 make -j${PROCESSORS} install || exit 1
|
| H A D | osx.sh | 25 PROCESSORS=${NPROCESSORS:-3}
27 make -j${PROCESSORS} check && make -j${PROCESSORS} install || exit 1
|
| H A D | nativeclient-x86_64.sh | 27 PROCESSORS=${NPROCESSORS:-3}
29 make -j${PROCESSORS} check && make -j${PROCESSORS} install || exit 1
|
| H A D | nativeclient-x86.sh | 27 PROCESSORS=${NPROCESSORS:-3}
29 make -j${PROCESSORS} check && make -j${PROCESSORS} install || exit 1
|
| H A D | nativeclient-pnacl.sh | 35 PROCESSORS=${NPROCESSORS:-3}
37 make -j${PROCESSORS} check && make -j${PROCESSORS} install || exit 1
|
| /freebsd-src/lib/libpmc/pmu-events/arch/x86/goldmontplus/ |
| H A D | frontend.json | 51 … "References per ICache line. This event counts differently than Intel processors based on Silverm…
58 …h target is to a new line.\r\nThis event counts differently than Intel processors based on Silverm…
63 …vailable in the ICache (hit). This event counts differently than Intel processors based on Silverm…
70 … cache line is in the ICache. This event counts differently than Intel processors based on Silverm…
75 …ailable in the ICache (miss). This event counts differently than Intel processors based on Silverm…
82 …he line is not in the ICache. This event counts differently than Intel processors based on Silverm…
|
| /freebsd-src/bin/nproc/ |
| H A D | nproc.1 | 11 .Nd print the number of processors
21 utility is used to print the number of processors limited to the
30 Count all processors currently online.
|
| /freebsd-src/sys/contrib/device-tree/Bindings/arm/ |
| H A D | arm,corstone1000.yaml | 16 processors.
18 Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
19 systems for M-Class (or other) processors for adding sensors, connectivity,
|
| /freebsd-src/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | intel,ixp4xx-interrupt.yaml | 8 title: Intel IXP4xx XScale Networking Processors Interrupt Controller
14 This interrupt controller is found in the Intel IXP4xx processors.
15 Some processors have 32 interrupts, some have up to 64 interrupts.
|
| /freebsd-src/sys/contrib/device-tree/Bindings/arm/keystone/ |
| H A D | ti,sci.yaml | 13 Texas Instrument's processors including those belonging to Keystone generation
14 of processors have separate hardware entity which is now responsible for the
21 on multiple processors including ones running Linux.
|
| H A D | ti,sci.txt | 4 Texas Instrument's processors including those belonging to Keystone generation
5 of processors have separate hardware entity which is now responsible for the
12 on multiple processors including ones running Linux.
14 See http://processors.wiki.ti.com/index.php/TISCI for protocol definition.
|
| /freebsd-src/share/man/man7/ |
| H A D | mitigations.7 | 329 Certain processors include features that prevent unintended access to memory
412 vulnerability exclusively affects AMD processors based on the Zen2
426 According to the vulnerability's discoverer, all Zen2-based processors are
437 to manufacturers no sooner than the end of 2023, except for Rome processors for
444 currently sets this bit by default on all Zen2 processors.
445 In the future, it might set it by default only on those Zen2 processors whose
456 Note that this setting is silently ignored when running on non-Zen2 processors
|
| /freebsd-src/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetPfmCounters.td | 62 // Processors can define how to measure cycles by defining a CycleCounter.
64 // Processors can define how to measure uops by defining a UopsCounter.
66 // Processors can define how to measure issued uops by defining IssueCounters.
|
| /freebsd-src/sys/contrib/device-tree/Bindings/hwlock/ |
| H A D | qcom-hwspinlock.txt | 3 The hardware block provides mutexes utilized between different processors on
4 the SoC as part of the communication protocol used by these processors.
|
| H A D | qcom-hwspinlock.yaml | 13 The hardware block provides mutexes utilized between different processors on
14 the SoC as part of the communication protocol used by these processors.
|
| /freebsd-src/sys/contrib/device-tree/Bindings/remoteproc/ |
| H A D | ti,omap-remoteproc.yaml | 25 Cortex-M4 processors.
109 processors that have them (OMAP4/OMAP5 DSPs do not have
149 processors. This will usually be a single timer if the
153 remote processors.
155 This property is mandatory on remote processors requiring
|
| /freebsd-src/sys/contrib/device-tree/Bindings/timer/ |
| H A D | intel,ixp4xx-timer.yaml | 8 title: Intel IXP4xx XScale Networking Processors Timers
13 description: This timer is found in the Intel IXP4xx processors.
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | LeonFeatures.td | 14 // UMAC and SMAC support for LEON3 and LEON4 processors.
22 "Enable UMAC and SMAC for LEON3 and LEON4 processors"
36 "Enable CASA instruction for LEON3 and LEON4 processors"
|
| /freebsd-src/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | intel,ixp4xx-gpio.txt | 1 Intel IXP4xx XScale Networking Processors GPIO
3 This GPIO controller is found in the Intel IXP4xx processors.
|