10b57cec5SDimitry Andric//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric// 90b57cec5SDimitry Andric// 100b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 110b57cec5SDimitry Andric 120b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 130b57cec5SDimitry Andric// Target-independent interfaces which we are implementing 140b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 150b57cec5SDimitry Andric 160b57cec5SDimitry Andricinclude "llvm/Target/Target.td" 170b57cec5SDimitry Andric 18*0fca6ea1SDimitry Andricinclude "ARMFeatures.td" 19*0fca6ea1SDimitry Andricinclude "ARMArchitectures.td" 200b57cec5SDimitry Andric 21e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 22e8d8bef9SDimitry Andric// Register File Description 23e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 24e8d8bef9SDimitry Andric 25e8d8bef9SDimitry Andricinclude "ARMRegisterInfo.td" 26e8d8bef9SDimitry Andricinclude "ARMRegisterBanks.td" 27e8d8bef9SDimitry Andricinclude "ARMCallingConv.td" 280b57cec5SDimitry Andric 290b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 300b57cec5SDimitry Andric// ARM schedules. 310b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 320b57cec5SDimitry Andric// 330b57cec5SDimitry Andricinclude "ARMPredicates.td" 340b57cec5SDimitry Andricinclude "ARMSchedule.td" 350b57cec5SDimitry Andric 360b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 37e8d8bef9SDimitry Andric// Instruction Descriptions 38e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 39e8d8bef9SDimitry Andric 40e8d8bef9SDimitry Andricinclude "ARMInstrInfo.td" 41e8d8bef9SDimitry Andricdef ARMInstrInfo : InstrInfo; 42e8d8bef9SDimitry Andric 43e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 44e8d8bef9SDimitry Andric// ARM schedules 45e8d8bef9SDimitry Andric// 46e8d8bef9SDimitry Andricinclude "ARMScheduleV6.td" 47e8d8bef9SDimitry Andricinclude "ARMScheduleA8.td" 48e8d8bef9SDimitry Andricinclude "ARMScheduleA9.td" 49e8d8bef9SDimitry Andricinclude "ARMScheduleSwift.td" 50e8d8bef9SDimitry Andricinclude "ARMScheduleR52.td" 51e8d8bef9SDimitry Andricinclude "ARMScheduleA57.td" 52e8d8bef9SDimitry Andricinclude "ARMScheduleM4.td" 53bdd1243dSDimitry Andricinclude "ARMScheduleM55.td" 54e8d8bef9SDimitry Andricinclude "ARMScheduleM7.td" 555f757f3fSDimitry Andricinclude "ARMScheduleM85.td" 56e8d8bef9SDimitry Andric 57*0fca6ea1SDimitry Andricinclude "ARMProcessors.td" 580b57cec5SDimitry Andric 590b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 600b57cec5SDimitry Andric// Declare the target which we are implementing 610b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 620b57cec5SDimitry Andric 630b57cec5SDimitry Andricdef ARMAsmWriter : AsmWriter { 640b57cec5SDimitry Andric string AsmWriterClassName = "InstPrinter"; 650b57cec5SDimitry Andric int PassSubtarget = 1; 660b57cec5SDimitry Andric int Variant = 0; 670b57cec5SDimitry Andric bit isMCAsmWriter = 1; 680b57cec5SDimitry Andric} 690b57cec5SDimitry Andric 700b57cec5SDimitry Andricdef ARMAsmParser : AsmParser { 710b57cec5SDimitry Andric bit ReportMultipleNearMisses = 1; 72*0fca6ea1SDimitry Andric let PreferSmallerInstructions = true; 730b57cec5SDimitry Andric} 740b57cec5SDimitry Andric 750b57cec5SDimitry Andricdef ARMAsmParserVariant : AsmParserVariant { 760b57cec5SDimitry Andric int Variant = 0; 770b57cec5SDimitry Andric string Name = "ARM"; 780b57cec5SDimitry Andric string BreakCharacters = "."; 790b57cec5SDimitry Andric} 800b57cec5SDimitry Andric 810b57cec5SDimitry Andricdef ARM : Target { 820b57cec5SDimitry Andric // Pull in Instruction Info. 830b57cec5SDimitry Andric let InstructionSet = ARMInstrInfo; 840b57cec5SDimitry Andric let AssemblyWriters = [ARMAsmWriter]; 850b57cec5SDimitry Andric let AssemblyParsers = [ARMAsmParser]; 860b57cec5SDimitry Andric let AssemblyParserVariants = [ARMAsmParserVariant]; 870b57cec5SDimitry Andric let AllowRegisterRenaming = 1; 880b57cec5SDimitry Andric} 89