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/llvm-project/llvm/test/ObjectYAML/MachO/
H A Dlazy_bind_opcode.yaml66 Imm: 2
70 Imm: 1
72 Imm: 0
75 Imm: 0
77 Imm: 0
79 Imm: 2
83 Imm: 1
85 Imm: 0
88 Imm: 0
90 Imm: 0
[all …]
H A Dbind_opcode.yaml66 Imm: 1
68 Imm: 0
71 Imm: 1
73 Imm: 2
77 Imm: 0
79 Imm: 0
82 Imm: 0
84 Imm: 0
87 Imm: 0
89 Imm: 2
[all …]
H A Dweak_bind_opcode.yaml66 Imm: 1
68 Imm: 0
71 Imm: 1
73 Imm: 2
77 Imm: 0
79 Imm: 0
82 Imm: 0
84 Imm: 0
87 Imm: 0
89 Imm: 2
[all …]
H A Dout_of_order_linkedit.yaml144 Imm: 1
146 Imm: 2
150 Imm: 0
154 Imm: 0
157 Imm: 1
160 Imm: 0
163 Imm: 1
166 Imm: 2
171 Imm: 0
174 Imm: 0
[all …]
/llvm-project/clang/test/InstallAPI/Inputs/Simple/
H A DSimple.yaml329 Imm: 1
331 Imm: 1
334 Imm: 0
337 Imm: 0
340 Imm: 2
342 Imm: 3
344 Imm: 0
347 Imm: 0
350 Imm: 2
352 Imm: 3
[all …]
/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AddressingModes.h73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) { in getShiftType() argument
74 switch ((Imm >> 6) & 0x7) { in getShiftType()
85 static inline unsigned getShiftValue(unsigned Imm) { in getShiftValue() argument
86 return Imm & 0x3f; in getShiftValue()
90 /// imm: 6-bit shift amount
97 /// {5-0} = imm
99 unsigned Imm) { in getShifterImm() argument
100 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!"); in getShifterImm()
110 return (STEnc << 6) | (Imm & 0x3f); in getShifterImm()
118 static inline unsigned getArithShiftValue(unsigned Imm) { in getArithShiftValue() argument
[all …]
/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlegalizer-info-validation.mir17 # DEBUG: G_ADD (opcode [[ADD_OPC:[0-9]+]]): 1 type index, 0 imm indices
19 # DEBUG-NEXT: .. the first uncovered imm index: 0, OK
21 # DEBUG-NEXT: G_SUB (opcode [[SUB_OPC:[0-9]+]]): 1 type index, 0 imm indices
24 # DEBUG-NEXT: .. the first uncovered imm index: 0, OK
26 # DEBUG-NEXT: G_MUL (opcode {{[0-9]+}}): 1 type index, 0 imm indices
28 # DEBUG-NEXT: .. the first uncovered imm index: 0, OK
30 # DEBUG-NEXT: G_SDIV (opcode {{[0-9]+}}): 1 type index, 0 imm indices
32 # DEBUG-NEXT: .. the first uncovered imm index: 0, OK
34 # DEBUG-NEXT: G_UDIV (opcode {{[0-9]+}}): 1 type index, 0 imm indices
37 # DEBUG-NEXT: .. the first uncovered imm inde
[all...]
/llvm-project/llvm/test/tools/llvm-lipo/Inputs/
H A Darmv7-slice-big.yaml389 Imm: 1
391 Imm: 2
395 Imm: 11
397 Imm: 2
399 Imm: 0
403 Imm: 2
405 Imm: 2
407 Imm: 0
412 Imm: 11
414 Imm: 0
[all …]
/llvm-project/llvm/test/tools/llvm-readtapi/
H A Dstubify-ehtypes.test420 Imm: 1
422 Imm: 1
425 Imm: 0
428 Imm: 0
431 Imm: 0
434 Imm: 2
437 Imm: 4
439 Imm: 1
441 Imm: 0
444 Imm: 3
[all …]
/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoC.td23 return isUInt<6>(Imm) && (Imm != 0);
24 return isUInt<5>(Imm) && (Imm != 0);
30 int64_t Imm;
31 if (!MCOp.evaluateAsConstantImm(Imm))
34 return isUInt<6>(Imm) && (Imm != 0);
35 return isUInt<5>(Imm) && (Imm !
[all...]
/llvm-project/llvm/test/CodeGen/X86/
H A Durem-seteq-nonzero.ll8 ; X86-NEXT: imull $-1431655765, {{[0-9]+}}(%esp), %eax # imm = 0xAAAAAAAB
9 ; X86-NEXT: addl $1431655765, %eax # imm = 0x55555555
10 ; X86-NEXT: cmpl $1431655765, %eax # imm = 0x55555555
16 ; X64-NEXT: imull $-1431655765, %edi, %eax # imm = 0xAAAAAAAB
17 ; X64-NEXT: addl $1431655765, %eax # imm = 0x55555555
18 ; X64-NEXT: cmpl $1431655765, %eax # imm = 0x55555555
29 ; X86-NEXT: imull $-1431655765, {{[0-9]+}}(%esp), %eax # imm = 0xAAAAAAAB
30 ; X86-NEXT: addl $-1431655766, %eax # imm = 0xAAAAAAAA
31 ; X86-NEXT: cmpl $1431655765, %eax # imm = 0x55555555
37 ; X64-NEXT: imull $-1431655765, %edi, %eax # imm = 0xAAAAAAAB
[all …]
H A Dis_fpclass.ll51 ; X86-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
53 ; X86-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
55 ; X86-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
63 ; X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
64 ; X64-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
66 ; X64-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
78 ; X86-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
80 ; X86-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000
82 ; X86-NEXT: cmpl $2139095041, %eax # imm = 0x7F800001
90 ; X64-NEXT: andl $2147483647, %eax # imm
[all...]
H A Disel-buildvector-sse.ll13 ; SSE-X64-NEXT: movabsq $3043555126665690671, %rcx # imm = 0x2A3CE143233A3E2F
15 ; SSE-X64-NEXT: movabsq $-2720818644236378031, %rcx # imm = 0xDA3DB5DBCC07E051
17 ; SSE-X64-NEXT: movabsq $3043545045377446960, %rcx # imm = 0x2A3CD817E79F7430
19 ; SSE-X64-NEXT: movabsq $-2715530310134355376, %rcx # imm = 0xDA507F9207A2AA50
26 ; SSE-X64-GISEL-NEXT: movl $128100944, %ecx # imm = 0x7A2AA50
27 ; SSE-X64-GISEL-NEXT: movl $-632258670, %edx # imm = 0xDA507F92
28 ; SSE-X64-GISEL-NEXT: movl $-408980432, %esi # imm = 0xE79F7430
29 ; SSE-X64-GISEL-NEXT: movl $708630551, %edi # imm = 0x2A3CD817
30 ; SSE-X64-GISEL-NEXT: movl $-871899055, %r8d # imm = 0xCC07E051
31 ; SSE-X64-GISEL-NEXT: movl $-633489957, %r9d # imm = 0xDA3DB5DB
[all …]
H A Dmemcpy-struct-by-value.ll22 ; NOFAST32-NEXT: subl $4100, %esp # imm = 0x1004
24 ; NOFAST32-NEXT: movl $1024, %ecx # imm = 0x400
28 ; NOFAST32-NEXT: addl $4100, %esp # imm = 0x1004
37 ; FAST32-NEXT: subl $4100, %esp # imm = 0x1004
39 ; FAST32-NEXT: movl $4096, %ecx # imm = 0x1000
43 ; FAST32-NEXT: addl $4100, %esp # imm = 0x1004
50 ; NOFAST-NEXT: subq $4104, %rsp # imm = 0x1008
52 ; NOFAST-NEXT: movl $512, %ecx # imm = 0x200
56 ; NOFAST-NEXT: addq $4104, %rsp # imm = 0x1008
61 ; FAST-NEXT: subq $4104, %rsp # imm
[all...]
/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrCDE.td16 let Name = "Imm"#width#"b";
21 ImmLeaf<i32, "{ return Imm >= 0 && Imm < (1 << "#width#"); }"> {
115 !con(params.Iops1, (ins imm_13b:$imm), params.PredOp),
116 !strconcat(iname, params.PAsm, "\t$coproc, $Rd, $imm"),
118 bits<13> imm;
122 let Inst{21-16} = imm{12-7};
124 let Inst{7} = imm{6};
125 let Inst{5-0} = imm{5-0};
131 !con(params.Iops2, (ins imm_9b:$imm), params.PredOp),
132 !strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $imm"),
[all …]
/llvm-project/llvm/lib/Target/Xtensa/Disassembler/
H A DXtensaDisassembler.cpp104 static DecodeStatus decodeCallOperand(MCInst &Inst, uint64_t Imm, in tryAddingSymbolicOperand()
106 assert(isUInt<18>(Imm) && "Invalid immediate"); in decodeCallOperand() argument
107 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Imm << 2))); in decodeCallOperand()
111 static DecodeStatus decodeJumpOperand(MCInst &Inst, uint64_t Imm, in decodeCallOperand()
113 assert(isUInt<18>(Imm) && "Invalid immediate"); in decodeJumpOperand() argument
114 Inst.addOperand(MCOperand::createImm(SignExtend64<18>(Imm))); in decodeJumpOperand()
118 static DecodeStatus decodeBranchOperand(MCInst &Inst, uint64_t Imm, in decodeJumpOperand()
125 assert(isUInt<12>(Imm) && "Invalid immediate"); in decodeBranchOperand()
126 if (!tryAddingSymbolicOperand(SignExtend64<12>(Imm) + 4 + Address, true, in decodeBranchOperand()
128 Inst.addOperand(MCOperand::createImm(SignExtend64<12>(Imm))); in decodeBranchOperand()
120 decodeBranchOperand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeBranchOperand() argument
141 decodeL32ROperand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeL32ROperand() argument
150 decodeImm8Operand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeImm8Operand() argument
157 decodeImm8_sh8Operand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeImm8_sh8Operand() argument
165 decodeImm12Operand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeImm12Operand() argument
172 decodeUimm4Operand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeUimm4Operand() argument
179 decodeUimm5Operand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeUimm5Operand() argument
186 decodeImm1_16Operand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeImm1_16Operand() argument
193 decodeShimm1_31Operand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeShimm1_31Operand() argument
203 decodeB4constOperand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeB4constOperand() argument
213 decodeB4constuOperand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeB4constuOperand() argument
222 decodeMem8Operand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeMem8Operand() argument
230 decodeMem16Operand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeMem16Operand() argument
238 decodeMem32Operand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeMem32Operand() argument
[all...]
/llvm-project/clang/include/clang/Basic/
H A Darm_cde.td65 !con((CDEIRInt<NAME> $cp), cgArgs, (? $imm))>;
68 cgArgs, (? $imm))>;
72 (seq !con((CDEIRInt<NAME # "d"> $cp), cgArgs, (? $imm)):$pair,
80 (? $imm)):$pair,
86 defm cx1 : CDE_CX_m<(args imm_13b:$imm), (args), (?)>;
87 defm cx2 : CDE_CX_m<(args imm_9b:$imm), (args u32:$n), (? $n)>;
88 defm cx3 : CDE_CX_m<(args imm_6b:$imm), (args u32:$n, u32:$m), (? $n, $m)>;
95 (bitcast !con((CDEIRInt<NAME, [f32]> $cp), cgArgs, (? $imm)),
99 (bitcast $acc, FScalar)), cgArgs, (? $imm)), Scalar)>;
103 (bitcast !con((CDEIRInt<NAME, [f64]> $cp), cgArgs, (? $imm)),
[all …]
/llvm-project/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp181 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) {
182 if (!isUInt<N>(Imm)) in decodeUImmOperand() argument
184 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
189 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) {
190 if (!isUInt<N>(Imm)) in decodeSImmOperand() argument
192 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
196 static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm,
199 return decodeUImmOperand<1>(Inst, Imm); in decodeU1ImmOperand()
202 static DecodeStatus decodeU2ImmOperand(MCInst &Inst, uint64_t Imm,
205 return decodeUImmOperand<2>(Inst, Imm); in decodeU2ImmOperand()
197 decodeU1ImmOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodeU1ImmOperand() argument
203 decodeU2ImmOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodeU2ImmOperand() argument
209 decodeU3ImmOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodeU3ImmOperand() argument
215 decodeU4ImmOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodeU4ImmOperand() argument
221 decodeU8ImmOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodeU8ImmOperand() argument
227 decodeU12ImmOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodeU12ImmOperand() argument
233 decodeU16ImmOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodeU16ImmOperand() argument
239 decodeU32ImmOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodeU32ImmOperand() argument
245 decodeS8ImmOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodeS8ImmOperand() argument
251 decodeS16ImmOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodeS16ImmOperand() argument
257 decodeS20ImmOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodeS20ImmOperand() argument
263 decodeS32ImmOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodeS32ImmOperand() argument
270 decodeLenOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodeLenOperand() argument
280 decodePCDBLOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,bool isBranch,const MCDisassembler * Decoder) decodePCDBLOperand() argument
293 decodePC12DBLBranchOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodePC12DBLBranchOperand() argument
299 decodePC16DBLBranchOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodePC16DBLBranchOperand() argument
305 decodePC24DBLBranchOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodePC24DBLBranchOperand() argument
311 decodePC32DBLBranchOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodePC32DBLBranchOperand() argument
317 decodePC32DBLOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodePC32DBLOperand() argument
[all...]
/llvm-project/llvm/test/tools/llvm-readtapi/Inputs/
H A Dobjc.yaml342 Imm: 1
344 Imm: 1
347 Imm: 1
349 Imm: 2
352 Imm: 0
355 Imm: 2
357 Imm: 3
359 Imm: 1
361 Imm: 3
363 Imm: 1
[all …]
/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrAliases.td93 // b<cond> $imm
94 def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"),
95 (BCOND brtarget:$imm, condVal)>;
97 // b<cond>,a $imm
98 def : InstAlias<!strconcat(!strconcat("b", cond), ",a $imm"),
99 (BCONDA brtarget:$imm, condVal)>;
101 // b<cond> %icc, $imm
102 def : InstAlias<!strconcat(!strconcat("b", cond), " %icc, $imm"),
103 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
105 // b<cond>,pt %icc, $imm
[all...]
/llvm-project/llvm/test/tools/llvm-objdump/ELF/ARM/
H A Dbranch-symbols.s1 @ RUN: llvm-mc < %s --triple=armv8a -mattr=+mve,+lob -filetype=obj | llvm-objdump --no-print-imm-…
2 @ RUN: llvm-mc < %s --triple=thumbv8a -mattr=+mve,+lob -filetype=obj | llvm-objdump --no-print-imm-…
10 @ CHECK: 0: b 0x0 <foo> @ imm = #-8
11 @ CHECK: 4: ble 0x0 <foo> @ imm = #-12
22 @ CHECK: 8: b 0x0 <foo> @ imm = #-12
23 @ CHECK: a: b.w 0x0 <foo> @ imm = #-14
24 @ CHECK: e: ble 0x0 <foo> @ imm = #-18
25 @ CHECK: 10: ble.w 0x0 <foo> @ imm = #-20
26 @ CHECK: 14: le 0x0 <foo> @ imm = #-24
27 @ CHECK: 18: le lr, 0x0 <foo> @ imm = #-28
[all …]
/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp60 int64_t Imm = Op.getImm(); in printU16ImmOperand()
61 if (isInt<16>(Imm) || isUInt<16>(Imm)) in printU16ImmOperand()
62 O << formatHex(static_cast<uint64_t>(Imm & 0xffff)); in printU16ImmOperand()
88 uint32_t Imm = MI->getOperand(OpNo).getImm();
89 if (Imm != 0) { in printU32ImmOperand()
96 O << formatDec(SignExtend32<24>(Imm)); in printNamedBit()
105 uint32_t Imm = MI->getOperand(OpNo).getImm(); in printOffset() local
106 if (Imm != 0) { in printOffset()
115 O << formatDec(SignExtend32(Imm, AMDGP in printOffset()
67 int64_t Imm = Op.getImm(); printU16ImmOperand() local
122 uint32_t Imm = MI->getOperand(OpNo).getImm(); printFlatOffset() local
183 auto Imm = MI->getOperand(OpNo).getImm(); printCPol() local
456 printImmediateInt16(uint32_t Imm,const MCSubtargetInfo & STI,raw_ostream & O) printImmediateInt16() argument
471 printImmediateFP16(uint32_t Imm,const MCSubtargetInfo & STI,raw_ostream & O) printImmediateFP16() argument
497 printImmediateBFloat16(uint32_t Imm,const MCSubtargetInfo & STI,raw_ostream & O) printImmediateBFloat16() argument
523 printImmediateBF16(uint32_t Imm,const MCSubtargetInfo & STI,raw_ostream & O) printImmediateBF16() argument
538 printImmediateF16(uint32_t Imm,const MCSubtargetInfo & STI,raw_ostream & O) printImmediateF16() argument
555 printImmediateV216(uint32_t Imm,uint8_t OpType,const MCSubtargetInfo & STI,raw_ostream & O) printImmediateV216() argument
592 printImmediateFloat32(uint32_t Imm,const MCSubtargetInfo & STI,raw_ostream & O) printImmediateFloat32() argument
622 printImmediate32(uint32_t Imm,const MCSubtargetInfo & STI,raw_ostream & O) printImmediate32() argument
637 printImmediate64(uint64_t Imm,const MCSubtargetInfo & STI,raw_ostream & O,bool IsFP) printImmediate64() argument
682 unsigned Imm = MI->getOperand(OpNo).getImm(); printBLGP() local
704 unsigned Imm = MI->getOperand(OpNo).getImm(); printCBSZ() local
714 unsigned Imm = MI->getOperand(OpNo).getImm(); printABID() local
1055 unsigned Imm = MI->getOperand(OpNo).getImm(); printDPP8() local
1068 unsigned Imm = MI->getOperand(OpNo).getImm(); printDPPCtrl() local
1174 unsigned Imm = MI->getOperand(OpNo).getImm(); printDppBoundCtrl() local
1183 unsigned Imm = MI->getOperand(OpNo).getImm(); printDppFI() local
1193 unsigned Imm = MI->getOperand(OpNo).getImm(); printSDWASel() local
1233 unsigned Imm = MI->getOperand(OpNo).getImm(); printSDWADstUnused() local
1433 auto Imm = MI->getOperand(OpNo).getImm() & 0x7; printIndexKey8bit() local
1443 auto Imm = MI->getOperand(OpNo).getImm() & 0x7; printIndexKey16bit() local
1453 unsigned Imm = MI->getOperand(OpNum).getImm(); printInterpSlot() local
1537 int Imm = MI->getOperand(OpNo).getImm(); printOModSI() local
1615 uint16_t Imm = MI->getOperand(OpNo).getImm(); printSwizzle() local
1806 uint16_t Imm = MI->getOperand(OpNo).getImm(); printEndpgm() local
1817 uint8_t Imm = MI->getOperand(OpNo).getImm(); printByteSel() local
[all...]
/llvm-project/llvm/test/MC/Lanai/
H A Dmemory.s12 ! CHECK-NEXT: <MCOperand Imm:0>
13 ! CHECK-NEXT: <MCOperand Imm:0>
20 ! CHECK-NEXT: <MCOperand Imm:0>
21 ! CHECK-NEXT: <MCOperand Imm:0>
28 ! CHECK-NEXT: <MCOperand Imm:0>
29 ! CHECK-NEXT: <MCOperand Imm:0>
36 ! CHECK-NEXT: <MCOperand Imm:291>
37 ! CHECK-NEXT: <MCOperand Imm:128>
44 ! CHECK-NEXT: <MCOperand Imm:-4>
45 ! CHECK-NEXT: <MCOperand Imm:128>
[all …]
/llvm-project/lld/test/MachO/
H A Dbind-opcodes.s17 # CHECK-NEXT: Imm: 0
20 # CHECK-NEXT: Imm: 1
23 # CHECK-NEXT: Imm: 2
26 # CHECK-NEXT: Imm: 2
30 # CHECK-NEXT: Imm: 0
34 # CHECK-NEXT: Imm: 0
38 # CHECK-NEXT: Imm: 0
42 # CHECK-NEXT: Imm: 0
46 # CHECK-NEXT: Imm: 0
49 # CHECK-NEXT: Imm: 0
[all …]
/llvm-project/llvm/test/Object/Inputs/MachO/
H A Drebase-bind-table-trailing-opcode.yaml244 Imm: 1
246 Imm: 1
249 Imm: 1
251 Imm: 2
254 Imm: 1
256 Imm: 1
259 Imm: 1
262 Imm: 0
265 Imm: 1
268 Imm: 1
[all …]

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