History log of /llvm-project/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp (Results 1 – 6 of 6)
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Revision tags: llvmorg-21-init
# d064d3fc 22-Jan-2025 Sylvestre Ledru <sylvestre@debian.org>

Revert "[Xtensa] Implement Windowed Register Option." (#123913)

Reverts llvm/llvm-project#121118
for causing #123817


# 0dcb16ef 21-Jan-2025 Andrei Safronov <andrei.safronov@espressif.com>

[Xtensa] Implement Windowed Register Option. (#121118)


Revision tags: llvmorg-19.1.7
# c6967efe 18-Dec-2024 Andrei Safronov <andrei.safronov@espressif.com>

[Xtensa] Implement Code Density Option. (#119639)

The Code Density option adds 16-bit encoding for frequently used
instructions.


Revision tags: llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3
# 432caca3 18-Feb-2023 Fangrui Song <i@maskray.me>

Simplify with hasFeature. NFC


Revision tags: llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7
# ff25800d 26-Dec-2022 Andrei Safronov <andrei.safronov@espressif.com>

[Xtensa 10/10] Add relaxations and fixups. Add rest part of Xtensa Core Instructions

Add branch/jump/call/l32r instructions and fixups support. Add R_XTENSA_32/R_XTENSA_SLOT0_OP
relocations in objec

[Xtensa 10/10] Add relaxations and fixups. Add rest part of Xtensa Core Instructions

Add branch/jump/call/l32r instructions and fixups support. Add R_XTENSA_32/R_XTENSA_SLOT0_OP
relocations in object files generation. Modify tests to support new instructions.
Add tests for relocations and fixups.

Differential Revision: https://reviews.llvm.org/D64836

show more ...


# 71199af1 26-Dec-2022 Andrei Safronov <andrei.safronov@espressif.com>

[Xtensa 9/10] Add basic support of Xtensa disassembler

Differential Revision: https://reviews.llvm.org/D64835