Searched full:aapcs (Results 1 – 25 of 54) sorted by relevance
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196 // AAPCS guarantees that sp will be 8-byte aligned on any public interface, in setTargetAttributes() 269 case ARMABIKind::AAPCS: in getABIDefaultCC() 320 if (getABIKind() == ARMABIKind::AAPCS || in classifyHomogeneousAggregate() 395 // WatchOS is adopting the 64-bit AAPCS rule on composite types: if they're in classifyArgumentType() 403 // The ABI alignment for APCS is 4-byte and for AAPCS at least 4-byte and at in classifyArgumentType() 409 getABIKind() == ARMABIKind::AAPCS) { in classifyArgumentType() 594 // Otherwise this is an AAPCS variant. in classifyReturnType() 599 // Check for homogeneous aggregates with AAPCS-VFP. in classifyReturnType() 617 // Return in 32 bit integer integer type (as if loaded by LDR, AAPCS 5.4) in classifyReturnType() 721 // Homogeneous aggregates for AAPCS in isLegalVectorType() [all...]
70 // FIXME: Enumerated types are variable width in straight AAPCS. in setABIAAPCS() 295 // The backend is hardwired to assume AAPCS for M-class processors, ensure in ARMTargetInfo() 300 setABI("aapcs"); in ARMTargetInfo() 308 setABI("aapcs"); in ARMTargetInfo() 320 setABI("aapcs-linux"); in ARMTargetInfo() 324 setABI("aapcs"); in ARMTargetInfo() 333 setABI("aapcs-linux"); in ARMTargetInfo() 335 setABI("aapcs"); in ARMTargetInfo() 346 // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS) in ARMTargetInfo() 371 // The defaults (above) are for AAPCS, chec in setABI() [all...]
61 // AAPCS f64 is in aligned register pairs164 // Allocate part of an AAPCS HFA or HVA. We assume that each member of the HA176 // AAPCS HFAs must have 1-4 elements, all of the same type in CC_ARM_AAPCS_Custom_Aggregate()263 // Mark all regs as unavailable (AAPCS rule C.2.vfp for VFP, C.6 for core) in CC_ARM_AAPCS_Custom_Aggregate()
126 // ARM AAPCS (EABI) Calling Convention, common parts156 // ARM AAPCS (EABI) Calling Convention203 // ARM AAPCS-VFP (EABI) Calling Convention274 // AAPCS, and also preserves all floating point registers.304 // When enforcing an AAPCS compliant frame chain, R11 is used as the frame306 // This AAPCS alternative makes sure the frame index slots match the push
134 else if (ABIName.starts_with("aapcs")) in computeTargetABI() 188 // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit in computeDataLayout()
545 return "aapcs"; in computeDefaultTargetABI() 551 return "aapcs"; in computeDefaultTargetABI() 563 return "aapcs-linux"; in computeDefaultTargetABI() 566 return "aapcs"; in computeDefaultTargetABI() 572 return "aapcs-linux"; in computeDefaultTargetABI() 573 return "aapcs"; in computeDefaultTargetABI()
29 #define COMPILER_RT_ABI __attribute__((__pcs__("aapcs")))35 #define AEABI_RTABI __attribute__((__pcs__("aapcs")))
259 static const char *strings[] = {"AAPCS", "AAPCS VFP", "Custom", in ABI_VFP_args()265 static const char *strings[] = {"AAPCS", "iWMMX", "Custom"}; in ABI_WMMX_args()
112 /// Helper function to check if we are targeting AAPCS.114 return Context.getTargetInfo().getABI().starts_with("aapcs"); in isAAPCS() 742 /// The AAPCS that defines that, when possible, bit-fields should754 /// -fno-aapcs-bitfield-width. in clipTailPadding() 770 // Info.StorageSize. Since AAPCS uses a different container size (width790 // packed struct. AAPCS does not define access rules for such cases, we let in determinePacked() 824 // The AAPCS acknowledges it and imposes no restritions when the in insertPadding()
439 AAPCS = 0,460 AAPCS = 1,416 AAPCS = 0, global() enumerator 435 AAPCS = 1, global() enumerator
85 /// single "field" within the LLVM struct type, taking into account the AAPCS
37 * To properly implement setjmp/longjmp for the ARM AAPCS ABI, it has to be
53 // required by AAPCS but is a requirement for HWASAN instrumented functions. in __hwasan_personality_wrapper()
27 // Ok, APCS and AAPCS agree on 32 bit args, so it's safe to use the same routine.
114 /// aapcs-linux.
95 __NDK_FPABI__ /* __attribute__((pcs("aapcs"))) on ARM */
178 // The backend is hardwired to assume AAPCS for M-class processors, ensure in useAAPCSForMachO() 430 // EABI is always AAPCS, and if it was not marked 'hard', it's softfp in getDefaultFloatABI() 805 if (FrameChainOption.starts_with("aapcs")) in getARMTargetFeatures() 806 Features.push_back("+aapcs-frame-chain"); in getARMTargetFeatures()
285 CC_AAPCS, // __attribute__((pcs("aapcs")))286 CC_AAPCS_VFP, // __attribute__((pcs("aapcs-vfp")))
426 /// Whether to follow the AAPCS enforcing at least one read before storing to a volatile bitfield432 /// Whether to not follow the AAPCS that enforces volatile bit-field access width to be
23 in a manner similar to that specified by AAPCS:
609 OS << " __attribute__((pcs(\"aapcs\")))"; in appendSubroutineNameAfter() 612 OS << " __attribute__((pcs(\"aapcs-vfp\")))"; in appendSubroutineNameAfter()
42 // In AAPCS, an SRet is passed in X8, not X0 like a normal pointer parameter.677 // Darwin variants of AAPCS.706 // guarantees more than a normal AAPCS function. x16 and x17 are used on the
157 /// normal C (AAPCS) calling convention for normal functions, but floats are
205 # (Latter thanks to __attribute__((pcs("aapcs"))) declaration.)