| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.h | 412 isSALU(uint16_t Opcode) isSALU() argument
420 isVALU(uint16_t Opcode) isVALU() argument
428 isImage(uint16_t Opcode) isImage() argument
436 isVMEM(uint16_t Opcode) isVMEM() argument
444 isSOP1(uint16_t Opcode) isSOP1() argument
452 isSOP2(uint16_t Opcode) isSOP2() argument
460 isSOPC(uint16_t Opcode) isSOPC() argument
468 isSOPK(uint16_t Opcode) isSOPK() argument
476 isSOPP(uint16_t Opcode) isSOPP() argument
484 isPacked(uint16_t Opcode) isPacked() argument
492 isVOP1(uint16_t Opcode) isVOP1() argument
500 isVOP2(uint16_t Opcode) isVOP2() argument
508 isVOP3(uint16_t Opcode) isVOP3() argument
516 isSDWA(uint16_t Opcode) isSDWA() argument
524 isVOPC(uint16_t Opcode) isVOPC() argument
532 isMUBUF(uint16_t Opcode) isMUBUF() argument
540 isMTBUF(uint16_t Opcode) isMTBUF() argument
548 isSMRD(uint16_t Opcode) isSMRD() argument
558 isDS(uint16_t Opcode) isDS() argument
566 isLDSDMA(uint16_t Opcode) isLDSDMA() argument
574 isGWS(uint16_t Opcode) isGWS() argument
584 isMIMG(uint16_t Opcode) isMIMG() argument
592 isVIMAGE(uint16_t Opcode) isVIMAGE() argument
600 isVSAMPLE(uint16_t Opcode) isVSAMPLE() argument
608 isGather4(uint16_t Opcode) isGather4() argument
623 isSegmentSpecificFLAT(uint16_t Opcode) isSegmentSpecificFLAT() argument
632 isFLATGlobal(uint16_t Opcode) isFLATGlobal() argument
640 isFLATScratch(uint16_t Opcode) isFLATScratch() argument
645 isFLAT(uint16_t Opcode) isFLAT() argument
661 isEXP(uint16_t Opcode) isEXP() argument
669 isAtomicNoRet(uint16_t Opcode) isAtomicNoRet() argument
677 isAtomicRet(uint16_t Opcode) isAtomicRet() argument
686 isAtomic(uint16_t Opcode) isAtomic() argument
699 isWQM(uint16_t Opcode) isWQM() argument
707 isDisableWQM(uint16_t Opcode) isDisableWQM() argument
722 isVGPRSpill(uint16_t Opcode) isVGPRSpill() argument
734 isSGPRSpill(uint16_t Opcode) isSGPRSpill() argument
740 isSpill(uint16_t Opcode) isSpill() argument
748 isWWMRegSpillOpcode(uint16_t Opcode) isWWMRegSpillOpcode() argument
755 isChainCallOpcode(uint64_t Opcode) isChainCallOpcode() argument
764 isDPP(uint16_t Opcode) isDPP() argument
772 isTRANS(uint16_t Opcode) isTRANS() argument
780 isVOP3P(uint16_t Opcode) isVOP3P() argument
788 isVINTRP(uint16_t Opcode) isVINTRP() argument
796 isMAI(uint16_t Opcode) isMAI() argument
813 isWMMA(uint16_t Opcode) isWMMA() argument
825 isSWMMAC(uint16_t Opcode) isSWMMAC() argument
829 isDOT(uint16_t Opcode) isDOT() argument
837 isLDSDIR(uint16_t Opcode) isLDSDIR() argument
845 isVINTERP(uint16_t Opcode) isVINTERP() argument
863 sopkIsZext(unsigned Opcode) sopkIsZext() argument
876 isScalarStore(uint16_t Opcode) isScalarStore() argument
884 isFixedSize(uint16_t Opcode) isFixedSize() argument
892 hasFPClamp(uint16_t Opcode) hasFPClamp() argument
912 usesFPDPRounding(uint16_t Opcode) usesFPDPRounding() argument
920 isFPAtomic(uint16_t Opcode) isFPAtomic() argument
931 isBarrierStart(unsigned Opcode) isBarrierStart() argument
943 doesNotReadTiedSource(uint16_t Opcode) doesNotReadTiedSource() argument
947 getNonSoftWaitcntOpcode(unsigned Opcode) getNonSoftWaitcntOpcode() argument
1105 getOpSize(uint16_t Opcode,unsigned OpNo) getOpSize() argument
1246 getMCOpcodeFromPseudo(unsigned Opcode) getMCOpcodeFromPseudo() argument
[all...] |
| /llvm-project/lldb/source/Plugins/Instruction/PPC64/ |
| H A D | EmulateInstructionPPC64.h | 71 struct Opcode { struct
80 Opcode *GetOpcodeForInstruction(uint32_t opcode); argument
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| /llvm-project/lldb/source/Plugins/Instruction/LoongArch/ |
| H A D | EmulateInstructionLoongArch.h | 66 struct Opcode { struct
74 Opcode *GetOpcodeForInstruction(uint32_t inst); argument
|
| /llvm-project/llvm/unittests/tools/llvm-exegesis/X86/ |
| H A D | SnippetGeneratorTest.cpp | 45 std::vector<CodeTemplate> checkAndGetCodeTemplates(unsigned Opcode) { in checkAndGetCodeTemplates() argument
73 const unsigned Opcode = X86::ADC16i16; in TEST_F() local
99 const unsigned Opcode in TEST_F() local
122 const unsigned Opcode = X86::VXORPSrr; TEST_F() local
147 const unsigned Opcode = X86::VXORPSrr; TEST_F() local
168 const unsigned Opcode = X86::VXORPSrr; TEST_F() local
199 const unsigned Opcode = X86::CMP64rr; TEST_F() local
220 const unsigned Opcode = X86::LAHF; TEST_F() local
239 const unsigned Opcode = X86::VCVTUSI642SDZrrb_Int; TEST_F() local
258 const unsigned Opcode = X86::CDQ; TEST_F() local
284 const unsigned Opcode = X86::CMOV32rr; TEST_F() local
324 const unsigned Opcode = X86::VFMADD132PDr; TEST_F() local
366 const unsigned Opcode = X86::CMOV_GR32; TEST_F() local
403 const unsigned Opcode = X86::MOV32rm; TEST_F() local
422 const unsigned Opcode = X86::MOV16ms; TEST_F() local
436 const unsigned Opcode = X86::MULX32rr; TEST_F() local
460 getInstr(unsigned Opcode) getInstr() argument
464 getInstructionTemplate(unsigned Opcode) getInstructionTemplate() argument
500 const unsigned Opcode = X86::MOVSB; TEST_F() local
[all...] |
| /llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFMISimplifyPatchable.cpp | 97 static bool isST(unsigned Opcode) { in isST()
102 static bool isSTX32(unsigned Opcode) { in isSTX32()
106 static bool isSTX64(unsigned Opcode) { in isSTX64()
111 static bool isLDX32(unsigned Opcode) { in isLDX32()
115 static bool isLDX64(unsigned Opcode) { in isLDX64()
120 static bool isLDSX(unsigned Opcode) { in isLDSX()
124 bool BPFMISimplifyPatchable::isLoadInst(unsigned Opcode) { in isLoadInst()
144 unsigned Opcode = DefInst->getOpcode(); in checkADDrr() local
178 unsigned Opcode) { in checkShift()
208 unsigned Opcode = I->getParent()->getOpcode(); in processCandidate() local
[all …]
|
| /llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.h | 146 isSPLSOpcode(unsigned Opcode) isSPLSOpcode() argument
160 isRMOpcode(unsigned Opcode) isRMOpcode() argument
170 isRRMOpcode(unsigned Opcode) isRRMOpcode() argument
|
| H A D | LanaiRegisterInfo.cpp | 69 isALUArithLoOpcode(unsigned Opcode) isALUArithLoOpcode() argument
85 getOppositeALULoOpcode(unsigned Opcode) getOppositeALULoOpcode() argument
108 getRRMOpcodeVariant(unsigned Opcode) getRRMOpcodeVariant() argument
|
| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVMakeCompressible.cpp | 98 static unsigned log2LdstWidth(unsigned Opcode) { in log2LdstWidth() argument
123 offsetMask(unsigned Opcode) offsetMask() argument
148 compressedLDSTOffsetMask(unsigned Opcode) compressedLDSTOffsetMask() argument
154 compressibleSPOffset(int64_t Offset,unsigned Opcode) compressibleSPOffset() argument
168 getBaseAdjustForCompression(int64_t Offset,unsigned Opcode) getBaseAdjustForCompression() argument
234 const unsigned Opcode = MI.getOpcode(); getRegImmPairPreventingCompression() local
341 unsigned Opcode = MI.getOpcode(); updateOperands() local
419 unsigned Opcode = RISCV::FPR32RegClass.contains(RegImm.Reg) runOnMachineFunction() local
[all...] |
| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetOpcodes.h | 30 inline bool isPreISelGenericOpcode(unsigned Opcode) { in isPreISelGenericOpcode()
36 inline bool isTargetSpecificOpcode(unsigned Opcode) { in isTargetSpecificOpcode()
42 inline bool isPreISelGenericOptimizationHint(unsigned Opcode) { in isPreISelGenericOptimizationHint()
|
| /llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| H A D | PPCPredicates.cpp | 17 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) { in InvertPredicate()
51 PPC::Predicate PPC::getSwappedPredicate(PPC::Predicate Opcode) { in getSwappedPredicate()
|
| /llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMUnwindOpAsm.h | 72 void EmitInt8(unsigned Opcode) { in EmitInt8()
77 void EmitInt16(unsigned Opcode) { in EmitInt16()
83 void emitBytes(const uint8_t *Opcode, size_t Size) { in emitBytes()
|
| /llvm-project/llvm/unittests/tools/llvm-exegesis/PowerPC/ |
| H A D | SnippetGeneratorTest.cpp | 35 std::vector<CodeTemplate> checkAndGetCodeTemplates(unsigned Opcode) { in checkAndGetCodeTemplates()
61 const unsigned Opcode = PPC::ADD8; in TEST_F() local
91 const unsigned Opcode = PPC::RLDIMI; in TEST_F() local
114 const unsigned Opcode = PPC::LDX; in TEST_F() local
|
| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZShortenInst.cpp | 110 bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) { in shortenOn0()
120 bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) { in shortenOn01()
132 bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) { in shortenOn001()
145 bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, unsigned Opcode) { in shortenOn001AddCC()
158 bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) { in shortenFPConv()
180 bool SystemZShortenInst::shortenFusedFPOp(MachineInstr &MI, unsigned Opcode) { in shortenFusedFPOp()
|
| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | MatchContext.h | 32 return Opcode == OpN->getOpcode(); in match() argument
111 // DAG.getNode(Opcode, DL, VT); } in getNode() argument
74 std::optional<unsigned> Opcode = ISD::getBaseOpcodeForVP( getRootBaseOpcode() local
119 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N1,SDValue N2) getNode() argument
127 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N1,SDValue N2,SDValue N3) getNode() argument
136 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue Operand,SDNodeFlags Flags) getNode() argument
145 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N1,SDValue N2,SDNodeFlags Flags) getNode() argument
154 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N1,SDValue N2,SDValue N3,SDNodeFlags Flags) getNode() argument
[all...] |
| /llvm-project/llvm/tools/llvm-readobj/ |
| H A D | ARMEHABIPrinter.h | 99 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_00xxxxxx() local
105 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_01xxxxxx() local
124 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011101() local
129 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011111() local
134 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_1001nnnn() local
139 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10100nnn() local
146 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10101nnn() local
153 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10110000() local
169 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10110010_uleb128() local
196 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_101101nn() local
[all …]
|
| /llvm-project/lldb/include/lldb/Core/ |
| H A D | Opcode.h | 43 Opcode(uint8_t inst, lldb::ByteOrder order) in Opcode() function
48 Opcode(uint16_t inst, lldb::ByteOrder order) in Opcode() function
53 Opcode(uint32_t inst, lldb::ByteOrder order) in Opcode() function
58 Opcode(uint64_t inst, lldb::ByteOrder order) in Opcode() function
63 Opcode(uint8_t *bytes, size_t length) in Opcode() function
|
| /llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVPostLegalizer.cpp | 56 isMetaInstrGET(unsigned Opcode) isMetaInstrGET() argument
64 mayBeInserted(unsigned Opcode) mayBeInserted() argument
86 const unsigned Opcode = I.getOpcode(); processNewInstrs() local
|
| /llvm-project/llvm/unittests/tools/llvm-exegesis/Mips/ |
| H A D | SnippetGeneratorTest.cpp | 35 std::vector<CodeTemplate> checkAndGetCodeTemplates(unsigned Opcode) { in checkAndGetCodeTemplates()
61 const unsigned Opcode = Mips::ADD; in TEST_F() local
106 const unsigned Opcode = Mips::LB; in TEST_F() local
|
| /llvm-project/llvm/lib/Target/Sparc/ |
| H A D | LeonPasses.cpp | 51 unsigned Opcode = MI.getOpcode(); runOnMachineFunction() local
86 unsigned Opcode = MI.getOpcode(); runOnMachineFunction() local
140 unsigned Opcode = MI.getOpcode(); runOnMachineFunction() local
|
| /llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInstrInfo.h | 63 const MCInstrDesc &get(unsigned Opcode) const { in get()
70 StringRef getName(unsigned Opcode) const { in getName()
|
| /llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegacyLegalizerInfo.h | 85 unsigned Opcode; member
180 setLegalizeScalarToDifferentSizeStrategy(const unsigned Opcode,const unsigned TypeIdx,SizeChangeStrategy S) setLegalizeScalarToDifferentSizeStrategy() argument
191 setLegalizeVectorElementToDifferentSizeStrategy(const unsigned Opcode,const unsigned TypeIdx,SizeChangeStrategy S) setLegalizeVectorElementToDifferentSizeStrategy() argument
311 setScalarAction(const unsigned Opcode,const unsigned TypeIndex,const SizeAndActionsVec & SizeAndActions) setScalarAction() argument
317 setPointerAction(const unsigned Opcode,const unsigned TypeIndex,const unsigned AddressSpace,const SizeAndActionsVec & SizeAndActions) setPointerAction() argument
334 setScalarInVectorAction(const unsigned Opcode,const unsigned TypeIndex,const SizeAndActionsVec & SizeAndActions) setScalarInVectorAction() argument
345 setVectorNumElementAction(const unsigned Opcode,const unsigned TypeIndex,const unsigned ElementSize,const SizeAndActionsVec & SizeAndActions) setVectorNumElementAction() argument
[all...] |
| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonTargetTransformInfo.cpp | 164 InstructionCost HexagonTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, in getMemoryOpCost() argument
222 HexagonTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *Src, in getMaskedMemoryOpCost() argument
239 unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, in getGatherScatterOpCost() argument
246 getInterleavedMemoryOpCost(unsigned Opcode,Type * VecTy,unsigned Factor,ArrayRef<unsigned> Indices,Align Alignment,unsigned AddressSpace,TTI::TargetCostKind CostKind,bool UseMaskForCond,bool UseMaskForGaps) getInterleavedMemoryOpCost() argument
258 getCmpSelInstrCost(unsigned Opcode,Type * ValTy,Type * CondTy,CmpInst::Predicate VecPred,TTI::TargetCostKind CostKind,const Instruction * I) getCmpSelInstrCost() argument
274 getArithmeticInstrCost(unsigned Opcode,Type * Ty,TTI::TargetCostKind CostKind,TTI::OperandValueInfo Op1Info,TTI::OperandValueInfo Op2Info,ArrayRef<const Value * > Args,const Instruction * CxtI) getArithmeticInstrCost() argument
294 getCastInstrCost(unsigned Opcode,Type * DstTy,Type * SrcTy,TTI::CastContextHint CCH,TTI::TargetCostKind CostKind,const Instruction * I) getCastInstrCost() argument
321 getVectorInstrCost(unsigned Opcode,Type * Val,TTI::TargetCostKind CostKind,unsigned Index,Value * Op0,Value * Op1) getVectorInstrCost() argument
[all...] |
| /llvm-project/llvm/lib/Target/RISCV/MCA/ |
| H A D | RISCVCustomBehaviour.cpp | 169 getEEWAndEMUL(unsigned Opcode, RISCVII::VLMUL LMUL, uint8_t SEW) { in getEEWAndEMUL()
208 bool opcodeHasEEWAndEMULInfo(unsigned short Opcode) { in opcodeHasEEWAndEMULInfo()
223 unsigned short Opcode = MCI.getOpcode(); in getSchedClassID() local
|
| /llvm-project/clang/lib/AST/Interp/ |
| H A D | Opcode.h | |
| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMSelectionDAGInfo.h | 23 static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) { in getShiftOpcForNode() argument
|