Lines Matching refs:OS
71 void runEnums(raw_ostream &OS);
74 void runMCDesc(raw_ostream &OS);
77 void runTargetHeader(raw_ostream &OS);
80 void runTargetDesc(raw_ostream &OS);
83 void run(raw_ostream &OS);
85 void debugDump(raw_ostream &OS);
88 void EmitRegMapping(raw_ostream &OS, const std::deque<CodeGenRegister> &Regs,
90 void EmitRegMappingTables(raw_ostream &OS,
93 void EmitRegUnitPressure(raw_ostream &OS, StringRef ClassName);
94 void emitComposeSubRegIndices(raw_ostream &OS, StringRef ClassName);
95 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, StringRef ClassName);
101 void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
109 emitSourceFileHeader("Target Register Enum Values", OS);
111 OS << "\n#ifdef GET_REGINFO_ENUM\n";
112 OS << "#undef GET_REGINFO_ENUM\n\n";
114 OS << "namespace llvm {\n\n";
116 OS << "class MCRegisterClass;\n"
121 OS << "namespace " << Namespace << " {\n";
122 OS << "enum : unsigned {\n NoRegister,\n";
125 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n";
128 OS << " NUM_TARGET_REGS // " << Registers.size() + 1 << "\n";
129 OS << "};\n";
131 OS << "} // end namespace " << Namespace << "\n";
140 OS << "\n// Register classes\n\n";
142 OS << "namespace " << Namespace << " {\n";
143 OS << "enum {\n";
145 OS << " " << RC.getIdName() << " = " << RC.EnumValue << ",\n";
146 OS << "\n};\n";
148 OS << "} // end namespace " << Namespace << "\n\n";
155 OS << "\n// Register alternate name indices\n\n";
157 OS << "namespace " << Namespace << " {\n";
158 OS << "enum {\n";
160 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
161 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
162 OS << "};\n";
164 OS << "} // end namespace " << Namespace << "\n\n";
169 OS << "\n// Subregister indices\n\n";
172 OS << "namespace " << Namespace << " {\n";
173 OS << "enum : uint16_t {\n NoSubRegister,\n";
176 OS << " " << Idx.getName() << ",\t// " << ++i << "\n";
177 OS << " NUM_TARGET_SUBREGS\n};\n";
179 OS << "} // end namespace " << Namespace << "\n\n";
182 OS << "// Register pressure sets enum.\n";
184 OS << "namespace " << Namespace << " {\n";
185 OS << "enum RegisterPressureSets {\n";
189 OS << " " << RegUnits.Name << " = " << i << ",\n";
191 OS << "};\n";
193 OS << "} // end namespace " << Namespace << '\n';
194 OS << '\n';
196 OS << "} // end namespace llvm\n\n";
197 OS << "#endif // GET_REGINFO_ENUM\n\n";
200 static void printInt(raw_ostream &OS, int Val) { OS << Val; }
202 void RegisterInfoEmitter::EmitRegUnitPressure(raw_ostream &OS,
207 OS << "/// Get the weight in units of pressure for this register class.\n"
213 OS << " {" << RC.getWeight(RegBank) << ", ";
215 OS << '0';
219 OS << RegBank.getRegUnitSetWeight(RegUnits);
221 OS << "}, \t// " << RC.getName() << "\n";
223 OS << " };\n"
235 OS << "/// Get the weight in units of pressure for this register unit.\n"
241 OS << " static const uint8_t RUWeightTable[] = {\n ";
246 OS << RU.Weight << ", ";
248 OS << "};\n"
251 OS << " // All register units have unit weight.\n"
254 OS << "}\n\n";
256 OS << "\n"
261 OS << "// Get the name of this register unit pressure set.\n"
269 OS << " \"" << RegUnits.Name << "\",\n";
271 OS << " };\n"
275 OS << "// Get the register unit pressure limit for this dimension.\n"
284 OS << " " << RegUnits.Weight << ", \t// " << i << ": " << RegUnits.Name
287 OS << " };\n"
310 OS << "/// Table of pressure sets per register class or unit.\n"
312 PSetsSeqs.emit(OS, printInt);
313 OS << "};\n\n";
315 OS << "/// Get the dimensions of register pressure impacted by this "
320 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32)
323 OS << PSetsSeqs.get(PSets[i]) << ",";
325 OS << "};\n"
329 OS << "/// Get the dimensions of register pressure impacted by this "
336 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32)
340 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx])
343 OS << "};\n"
375 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
399 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n";
404 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
405 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
406 OS << I << "Dwarf2L[]";
409 OS << " = {\n";
422 OS << " { " << I.first << "U, " << getQualifiedName(I.second)
425 OS << "};\n";
427 OS << ";\n";
432 OS << "extern const unsigned " << Namespace
435 OS << " = std::size(" << Namespace
438 OS << ";\n\n";
468 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
469 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
470 OS << i << "L2Dwarf[]";
472 OS << " = {\n";
480 OS << " { " << getQualifiedName(DwarfRegNum.first) << ", " << RegNo
483 OS << "};\n";
485 OS << ";\n";
490 OS << "extern const unsigned " << Namespace
493 OS << " = std::size(" << Namespace
496 OS << ";\n\n";
502 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
519 OS << " switch (";
521 OS << "DwarfFlavour";
523 OS << "EHFlavour";
524 OS << ") {\n"
529 OS << " case " << i << ":\n";
530 OS << " ";
532 OS << "RI->";
537 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, ";
539 OS << "false";
541 OS << "true";
542 OS << ");\n";
543 OS << " break;\n";
545 OS << " }\n";
550 OS << " switch (";
552 OS << "DwarfFlavour";
554 OS << "EHFlavour";
555 OS << ") {\n"
560 OS << " case " << i << ":\n";
561 OS << " ";
563 OS << "RI->";
568 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, ";
570 OS << "false";
572 OS << "true";
573 OS << ");\n";
574 OS << " break;\n";
576 OS << " }\n";
582 static void printBitVectorAsHex(raw_ostream &OS, const BitVector &Bits,
590 OS << format("0x%0*x, ", Digits, Value);
605 void print(raw_ostream &OS) { printBitVectorAsHex(OS, Values, 8); }
608 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
609 OS << getEnumName(VT);
612 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) {
613 OS << (Idx ? Idx->EnumValue : 0);
654 static void printDiff16(raw_ostream &OS, int16_t Val) { OS << Val; }
656 static void printMask(raw_ostream &OS, LaneBitmask Val) {
657 OS << "LaneBitmask(0x" << PrintLaneMask(Val) << ')';
680 void RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS,
683 OS << "unsigned " << ClassName
718 OS << " static const " << getMinimalTypeForRange(Rows.size(), 32)
721 OS << RowMap[i] << ", ";
722 OS << "\n };\n";
726 OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1, 32)
729 OS << " { ";
732 OS << Rows[r][i]->getQualifiedName() << ", ";
734 OS << "0, ";
735 OS << "},\n";
737 OS << " };\n\n";
739 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << "); (void) IdxA;\n"
742 OS << " return Rows[RowMap[IdxA]][IdxB];\n";
744 OS << " return Rows[0][IdxB];\n";
745 OS << "}\n\n";
748 void RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS,
778 OS << " struct MaskRolOp {\n"
785 OS << " ";
789 printMask(OS << "{ ", P.Mask);
790 OS << format(", %2u }, ", P.RotateLeft);
792 OS << "{ LaneBitmask::getNone(), 0 }";
794 OS << ", ";
795 OS << " // Sequence " << Idx << "\n";
800 OS << " };\n"
804 OS << " ";
805 OS << SubReg2SequenceIndexMap[i];
807 OS << ",";
808 OS << " // to " << SubRegIndices[i].getName() << "\n";
810 OS << " };\n\n";
812 OS << "LaneBitmask " << ClassName
833 OS << "LaneBitmask " << ClassName
858 void RegisterInfoEmitter::runMCDesc(raw_ostream &OS) {
859 emitSourceFileHeader("MC Register Information", OS);
861 OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
862 OS << "#undef GET_REGINFO_MC_DESC\n\n";
929 OS << "namespace llvm {\n\n";
934 OS << "extern const int16_t " << TargetName << "RegDiffLists[] = {\n";
935 DiffSeqs.emit(OS, printDiff16);
936 OS << "};\n\n";
939 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n";
940 LaneMaskSeqs.emit(OS, printMask);
941 OS << "};\n\n";
944 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n";
945 SubRegIdxSeqs.emit(OS, printSubRegIndex);
946 OS << "};\n\n";
950 RegStrings.emitStringLiteralDef(OS, Twine("extern const char ") + TargetName +
953 OS << "extern const MCRegisterDesc " << TargetName
955 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0, 0, 0 },\n";
966 OS << " { " << RegStrings.get(std::string(Reg.getName())) << ", "
974 OS << "};\n\n"; // End of register descriptors...
978 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n";
983 OS << " { ";
986 OS << LS << getQualifiedName(R->TheDef);
987 OS << " },\n";
989 OS << "};\n\n";
994 OS << "namespace { // Register classes...\n";
1009 OS << " // " << Name << " Register Class...\n"
1012 OS << getQualifiedName(Reg) << ", ";
1014 OS << "\n };\n\n";
1016 OS << " // " << Name << " Bit set.\n"
1022 BVE.print(OS);
1023 OS << "\n };\n\n";
1026 OS << "} // end anonymous namespace\n\n";
1030 OS, Twine("extern const char ") + TargetName + "RegClassStrings[]");
1032 OS << "extern const MCRegisterClass " << TargetName
1044 OS << " { " << RCName << ", " << RCBitsName << ", "
1052 OS << "};\n\n";
1054 EmitRegMappingTables(OS, Regs, false);
1057 OS << "extern const uint16_t " << TargetName;
1058 OS << "RegEncodingTable[] = {\n";
1060 OS << " 0,\n";
1069 OS << " " << Value << ",\n";
1071 OS << "};\n"; // End of HW encoding table
1074 OS << "static inline void Init" << TargetName
1087 EmitRegMapping(OS, Regs, false);
1089 OS << "}\n\n";
1091 OS << "} // end namespace llvm\n\n";
1092 OS << "#endif // GET_REGINFO_MC_DESC\n\n";
1095 void RegisterInfoEmitter::runTargetHeader(raw_ostream &OS) {
1096 emitSourceFileHeader("Register Information Header Fragment", OS);
1098 OS << "\n#ifdef GET_REGINFO_HEADER\n";
1099 OS << "#undef GET_REGINFO_HEADER\n\n";
1104 OS << "#include \"llvm/CodeGen/TargetRegisterInfo.h\"\n\n";
1106 OS << "namespace llvm {\n\n";
1108 OS << "class " << TargetName << "FrameLowering;\n\n";
1110 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
1115 OS << " unsigned composeSubRegIndicesImpl"
1126 OS << " const RegClassWeight &getRegClassWeight("
1155 OS << " const TargetRegisterClass *getPhysRegBaseClass(MCRegister Reg) "
1159 OS << "};\n\n";
1162 OS << "namespace " << RegisterClasses.front().Namespace
1169 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n";
1171 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n";
1173 OS << "} // end namespace llvm\n\n";
1174 OS << "#endif // GET_REGINFO_HEADER\n\n";
1180 void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS) {
1181 emitSourceFileHeader("Target Register and Register Classes Information", OS);
1183 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
1184 OS << "#undef GET_REGINFO_TARGET_DESC\n\n";
1186 OS << "namespace llvm {\n\n";
1189 OS << "extern const MCRegisterClass " << Target.getName()
1223 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n";
1224 VTSeqs.emit(OS, printSimpleValueType);
1225 OS << "};\n";
1228 OS << "\nstatic const char *SubRegIndexNameTable[] = { \"";
1231 OS << Idx.getName();
1232 OS << "\", \"";
1234 OS << "\" };\n\n";
1237 OS << "static const TargetRegisterInfo::SubRegCoveredBits "
1240 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n";
1243 OS << " { " << Range.Offset << ", " << Range.Size << " },\t// "
1247 OS << "};\n\n";
1250 OS << "\nstatic const LaneBitmask SubRegIndexLaneMaskTable[] = {\n "
1253 printMask(OS << " ", Idx.LaneMask);
1254 OS << ", // " << Idx.getName() << '\n';
1256 OS << " };\n\n";
1258 OS << "\n";
1262 OS << "\nstatic const TargetRegisterInfo::RegClassInfo RegClassInfos[]"
1266 OS << " // Mode = " << M << " (";
1268 OS << "Default";
1270 OS << CGH.getMode(M).Name;
1271 OS << ")\n";
1277 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", "
1283 OS << ", /*VTLists+*/" << VTSeqs.get(VTs) << " }, // "
1287 OS << "};\n";
1314 OS << "static const uint32_t " << RC.getName()
1316 printBitVectorAsHex(OS, RC.getSubClasses(), 32);
1327 OS << "\n ";
1328 printBitVectorAsHex(OS, MaskBV, 32);
1329 OS << "// " << Idx.getName();
1332 OS << "\n};\n\n";
1335 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n";
1337 SuperRegIdxSeqs.emit(OS, printSubRegIndex);
1338 OS << "};\n\n";
1348 OS << "static unsigned const " << RC.getName() << "Superclasses[] = {\n";
1350 OS << " " << Super->getQualifiedIdName() << ",\n";
1351 OS << "};\n\n";
1357 OS << "\nstatic inline unsigned " << RC.getName()
1365 OS << " static const MCPhysReg AltOrder" << oi << "[] = {";
1367 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
1368 OS << " };\n";
1371 OS << " const MCRegisterClass &MCR = " << Target.getName()
1377 OS << "),\n ArrayRef<MCPhysReg>(";
1379 OS << "),\n ArrayRef(AltOrder" << oi;
1380 OS << ")\n };\n const unsigned Select = " << RC.getName()
1387 OS << "\nnamespace " << RegisterClasses.front().Namespace
1391 OS << " extern const TargetRegisterClass " << RC.getName()
1396 printMask(OS, RC.LaneMask);
1397 OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n "
1405 OS << "nullptr, ";
1407 OS << RC.getName() << "Superclasses, ";
1408 OS << RC.getSuperClasses().size() << ",\n ";
1410 OS << "nullptr\n";
1412 OS << RC.getName() << "GetRawAllocationOrder\n";
1413 OS << " };\n\n";
1416 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n";
1419 OS << "\nnamespace {\n";
1420 OS << " const TargetRegisterClass *const RegisterClasses[] = {\n";
1422 OS << " &" << RC.getQualifiedName() << "RegClass,\n";
1423 OS << " };\n";
1424 OS << "} // end anonymous namespace\n";
1454 OS << "\nstatic const uint8_t "
1458 OS << AllRegCostPerUse[J] << ", ";
1460 OS << "};\n\n";
1462 OS << "\nstatic const bool "
1465 OS << (InAllocClass[I] ? "true" : "false") << ", ";
1467 OS << "};\n\n";
1469 OS << "\nstatic const TargetRegisterInfoDesc " << TargetName
1471 OS << "CostPerUseTable, " << NumRegCosts << ", "
1473 OS << "};\n\n"; // End of register descriptors...
1481 emitComposeSubRegIndices(OS, ClassName);
1482 emitComposeSubRegIndexLaneMask(OS, ClassName);
1487 OS << "const TargetRegisterClass *" << ClassName
1493 OS << " static const uint8_t Table[";
1495 OS << " static const uint16_t Table[";
1498 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n";
1500 OS << " {\t// " << RC.getName() << "\n";
1503 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName()
1506 OS << " 0,\t// " << Idx.getName() << "\n";
1508 OS << " },\n";
1510 OS << " };\n assert(RC && \"Missing regclass\");\n"
1517 OS << "const TargetRegisterClass *" << ClassName
1524 OS << " static const uint8_t Table[";
1526 OS << " static const uint16_t Table[";
1530 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n";
1533 OS << " {\t// " << RC.getName() << '\n';
1544 OS << " " << EnumValue << ",\t// " << RC.getName() << ':'
1549 OS << " -> " << SubRegClass->getName();
1552 OS << '\n';
1555 OS << " },\n";
1557 OS << " };\n assert(RC && \"Missing regclass\");\n"
1564 EmitRegUnitPressure(OS, ClassName);
1588 OS << "\n// Register to base register class mapping\n\n";
1589 OS << "\n";
1590 OS << "const TargetRegisterClass *" << ClassName
1593 OS << " static const uint16_t InvalidRegClassID = UINT16_MAX;\n\n";
1594 OS << " static const uint16_t Mapping[" << Regs.size() + 1 << "] = {\n";
1595 OS << " InvalidRegClassID, // NoRegister\n";
1605 OS << " "
1609 OS << " };\n\n"
1620 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
1621 OS << "extern const int16_t " << TargetName << "RegDiffLists[];\n";
1622 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[];\n";
1623 OS << "extern const char " << TargetName << "RegStrings[];\n";
1624 OS << "extern const char " << TargetName << "RegClassStrings[];\n";
1625 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n";
1626 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n";
1627 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n";
1629 EmitRegMappingTables(OS, Regs, true);
1631 OS << ClassName << "::\n"
1640 printMask(OS, RegBank.CoveringLanes);
1641 OS << ", RegClassInfos, VTLists, HwMode) {\n"
1655 EmitRegMapping(OS, Regs, true);
1657 OS << "}\n\n";
1667 OS << "static const MCPhysReg " << CSRSet->getName() << "_SaveList[] = { ";
1669 OS << getQualifiedName(Reg) << ", ";
1670 OS << "0 };\n";
1692 OS << "static const uint32_t " << CSRSet->getName() << "_RegMask[] = { ";
1693 printBitVectorAsHex(OS, Covered, 32);
1694 OS << "};\n";
1696 OS << "\n\n";
1698 OS << "ArrayRef<const uint32_t *> " << ClassName
1701 OS << " static const uint32_t *const Masks[] = {\n";
1703 OS << " " << CSRSet->getName() << "_RegMask,\n";
1704 OS << " };\n";
1705 OS << " return ArrayRef(Masks);\n";
1707 OS << " return {};\n";
1709 OS << "}\n\n";
1713 OS << "bool " << ClassName << "::\n"
1720 OS << " " << RC->getQualifiedName()
1724 OS << " false;\n";
1725 OS << "}\n\n";
1727 OS << "bool " << ClassName << "::\n"
1734 OS << " " << RC->getQualifiedName()
1738 OS << " false;\n";
1739 OS << "}\n\n";
1741 OS << "bool " << ClassName << "::\n"
1748 OS << " " << RC->getQualifiedName()
1752 OS << " false;\n";
1753 OS << "}\n\n";
1755 OS << "bool " << ClassName << "::\n"
1762 OS << " " << RC->getQualifiedName()
1766 OS << " false;\n";
1767 OS << "}\n\n";
1769 OS << "bool " << ClassName << "::\n"
1774 OS << " PhysReg == " << getQualifiedName(Reg.TheDef) << " ||\n";
1775 OS << " false;\n";
1776 OS << "}\n\n";
1778 OS << "ArrayRef<const char *> " << ClassName
1781 OS << " static const char *Names[] = {\n";
1783 OS << " " << '"' << CSRSet->getName() << '"' << ",\n";
1784 OS << " };\n";
1785 OS << " return ArrayRef(Names);\n";
1787 OS << " return {};\n";
1789 OS << "}\n\n";
1791 OS << "const " << TargetName << "FrameLowering *\n"
1798 OS << "} // end namespace llvm\n\n";
1799 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
1802 void RegisterInfoEmitter::run(raw_ostream &OS) {
1805 runEnums(OS);
1808 runMCDesc(OS);
1811 runTargetHeader(OS);
1814 runTargetDesc(OS);
1820 void RegisterInfoEmitter::debugDump(raw_ostream &OS) {
1830 OS << "RegisterClass " << RC.getName() << ":\n";
1831 OS << "\tSpillSize: {";
1833 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillSize;
1834 OS << " }\n\tSpillAlignment: {";
1836 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillAlignment;
1837 OS << " }\n\tNumRegs: " << RC.getMembers().size() << '\n';
1838 OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n';
1839 OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n';
1840 OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n';
1841 OS << "\tAllocatable: " << RC.Allocatable << '\n';
1842 OS << "\tAllocationPriority: " << unsigned(RC.AllocationPriority) << '\n';
1843 OS << "\tBaseClassOrder: " << RC.getBaseClassOrder() << '\n';
1844 OS << "\tRegs:";
1846 OS << " " << R->getName();
1848 OS << '\n';
1849 OS << "\tSubClasses:";
1854 OS << " " << SRC.getName();
1856 OS << '\n';
1857 OS << "\tSuperClasses:";
1859 OS << " " << SRC->getName();
1861 OS << '\n';
1865 OS << "SubRegIndex " << SRI.getName() << ":\n";
1866 OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n';
1867 OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n';
1868 OS << "\tOffset: {";
1870 OS << ' ' << getModeName(M) << ':' << SRI.Range.get(M).Offset;
1871 OS << " }\n\tSize: {";
1873 OS << ' ' << getModeName(M) << ':' << SRI.Range.get(M).Size;
1874 OS << " }\n";
1878 OS << "Register " << R.getName() << ":\n";
1879 OS << "\tCostPerUse: ";
1881 OS << Cost << " ";
1882 OS << '\n';
1883 OS << "\tCoveredBySubregs: " << R.CoveredBySubRegs << '\n';
1884 OS << "\tHasDisjunctSubRegs: " << R.HasDisjunctSubRegs << '\n';
1886 OS << "\tSubReg " << SubIdx->getName() << " = " << SubReg->getName()