Lines Matching refs:attribute

318 ; CHECK: .attribute 4, 16
320 ; RV32M: .attribute 5, "rv32i2p1_m2p0_zmmul1p0"
321 ; RV32ZMMUL: .attribute 5, "rv32i2p1_zmmul1p0"
322 ; RV32MZMMUL: .attribute 5, "rv32i2p1_m2p0_zmmul1p0"
323 ; RV32A: .attribute 5, "rv32i2p1_a2p1_zaamo1p0_zalrsc1p0"
324 ; RV32B: .attribute 5, "rv32i2p1_b1p0_zba1p0_zbb1p0_zbs1p0"
325 ; RV32F: .attribute 5, "rv32i2p1_f2p2_zicsr2p0"
326 ; RV32D: .attribute 5, "rv32i2p1_f2p2_d2p2_zicsr2p0"
327 ; RV32C: .attribute 5, "rv32i2p1_c2p0"
328 ; RV32ZIHINTPAUSE: .attribute 5, "rv32i2p1_zihintpause2p0"
329 ; RV32ZIHINTNTL: .attribute 5, "rv32i2p1_zihintntl1p0"
330 ; RV32ZFHMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfhmin1p0"
331 ; RV32ZFH: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfh1p0_zfhmin1p0"
332 ; RV32ZBA: .attribute 5, "rv32i2p1_zba1p0"
333 ; RV32ZBB: .attribute 5, "rv32i2p1_zbb1p0"
334 ; RV32ZBC: .attribute 5, "rv32i2p1_zbc1p0"
335 ; RV32ZBS: .attribute 5, "rv32i2p1_zbs1p0"
336 ; RV32V: .attribute 5, "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
337 ; RV32H: .attribute 5, "rv32i2p1_h1p0"
338 ; RV32COMBINED: .attribute 5, "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
339 ; RV32ZBKB: .attribute 5, "rv32i2p1_zbkb1p0"
340 ; RV32ZBKC: .attribute 5, "rv32i2p1_zbkc1p0"
341 ; RV32ZBKX: .attribute 5, "rv32i2p1_zbkx1p0"
342 ; RV32ZKND: .attribute 5, "rv32i2p1_zknd1p0"
343 ; RV32ZKNE: .attribute 5, "rv32i2p1_zkne1p0"
344 ; RV32ZKNH: .attribute 5, "rv32i2p1_zknh1p0"
345 ; RV32ZKSED: .attribute 5, "rv32i2p1_zksed1p0"
346 ; RV32ZKSH: .attribute 5, "rv32i2p1_zksh1p0"
347 ; RV32ZKR: .attribute 5, "rv32i2p1_zkr1p0"
348 ; RV32ZKN: .attribute 5, "rv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
349 ; RV32ZKS: .attribute 5, "rv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
350 ; RV32ZKT: .attribute 5, "rv32i2p1_zkt1p0"
351 ; RV32ZK: .attribute 5, "rv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
352 ; RV32COMBINEINTOZK: .attribute 5, "rv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
353 ; RV32COMBINEINTOZKN: .attribute 5, "rv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
354 ; RV32COMBINEINTOZKS: .attribute 5, "rv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
355 ; RV32ZICBOM: .attribute 5, "rv32i2p1_zicbom1p0"
356 ; RV32ZICBOZ: .attribute 5, "rv32i2p1_zicboz1p0"
357 ; RV32ZICBOP: .attribute 5, "rv32i2p1_zicbop1p0"
358 ; RV32SHA: .attribute 5, "rv32i2p1_h1p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssstateen1p0"
359 ; RV32SHCOUNTERENW: .attribute 5, "rv32i2p1_shcounterenw1p0"
360 ; RV32SHGATPA: .attribute 5, "rv32i2p1_shgatpa1p0"
361 ; RV32SHVSATPA: .attribute 5, "rv32i2p1_shvsatpa1p0"
362 ; RV32SSCCFG: .attribute 5, "rv32i2p1_ssccfg1p0"
363 ; RV32SSCCPTR: .attribute 5, "rv32i2p1_ssccptr1p0"
364 ; RV32SSCOFPMF: .attribute 5, "rv32i2p1_sscofpmf1p0"
365 ; RV32SSCOUNTERENW: .attribute 5, "rv32i2p1_sscounterenw1p0"
366 ; RV32SMSTATEEN: .attribute 5, "rv32i2p1_smstateen1p0"
367 ; RV32SSSTATEEN: .attribute 5, "rv32i2p1_ssstateen1p0"
368 ; RV32SSSTRICT: .attribute 5, "rv32i2p1_ssstrict1p0"
369 ; RV32SSTC: .attribute 5, "rv32i2p1_sstc1p0"
370 ; RV32SHTVALA: .attribute 5, "rv32i2p1_shtvala1p0"
371 ; RV32SHVSTVALA: .attribute 5, "rv32i2p1_shvstvala1p0"
372 ; RV32SHVSTVECD: .attribute 5, "rv32i2p1_shvstvecd1p0"
373 ; RV32SSTVALA: .attribute 5, "rv32i2p1_sstvala1p0"
374 ; RV32SSTVECD: .attribute 5, "rv32i2p1_sstvecd1p0"
375 ; RV32SSU64XL: .attribute 5, "rv32i2p1_ssu64xl1p0"
376 ; RV32SVADE: .attribute 5, "rv32i2p1_svade1p0"
377 ; RV32SVADU: .attribute 5, "rv32i2p1_svadu1p0"
378 ; RV32SVBARE: .attribute 5, "rv32i2p1_svbare1p0"
379 ; RV32SVNAPOT: .attribute 5, "rv32i2p1_svnapot1p0"
380 ; RV32SVPBMT: .attribute 5, "rv32i2p1_svpbmt1p0"
381 ; RV32SVUKTE: .attribute 5, "rv32i2p1_svukte0p3"
382 ; RV32SVVPTC: .attribute 5, "rv32i2p1_svvptc1p0"
383 ; RV32SVINVAL: .attribute 5, "rv32i2p1_svinval1p0"
384 ; RV32XCVALU: .attribute 5, "rv32i2p1_xcvalu1p0"
385 ; RV32XCVBITMANIP: .attribute 5, "rv32i2p1_xcvbitmanip1p0"
386 ; RV32XCVELW: .attribute 5, "rv32i2p1_xcvelw1p0"
387 ; RV32XCVMAC: .attribute 5, "rv32i2p1_xcvmac1p0"
388 ; RV32XCVMEM: .attribute 5, "rv32i2p1_xcvmem1p0"
389 ; RV32XCVSIMD: .attribute 5, "rv32i2p1_xcvsimd1p0"
390 ; RV32XCVBI: .attribute 5, "rv32i2p1_xcvbi1p0"
391 ; RV32XSFVFWMACCQQQ: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0_xsfvfwmaccqqq1p0"
392 ; RV32XTHEADCMO: .attribute 5, "rv32i2p1_xtheadcmo1p0"
393 ; RV32XTHEADCONDMOV: .attribute 5, "rv32i2p1_xtheadcondmov1p0"
394 ; RV32XTHEADFMEMIDX: .attribute 5, "rv32i2p1_xtheadfmemidx1p0"
395 ; RV32XTHEADMAC: .attribute 5, "rv32i2p1_xtheadmac1p0"
396 ; RV32XTHEADMEMIDX: .attribute 5, "rv32i2p1_xtheadmemidx1p0"
397 ; RV32XTHEADMEMPAIR: .attribute 5, "rv32i2p1_xtheadmempair1p0"
398 ; RV32XTHEADSYNC: .attribute 5, "rv32i2p1_xtheadsync1p0"
399 ; RV32XWCHC: .attribute 5, "rv32i2p1_xwchc2p2"
400 ; RV32XQCIA: .attribute 5, "rv32i2p1_xqcia0p2"
401 ; RV32XQCIAC: .attribute 5, "rv32i2p1_zca1p0_xqciac0p3"
402 ; RV32XQCICLI: .attribute 5, "rv32i2p1_xqcicli0p2"
403 ; RV32XQCICM: .attribute 5, "rv32i2p1_zca1p0_xqcicm0p2"
404 ; RV32XQCICS: .attribute 5, "rv32i2p1_xqcics0p2"
405 ; RV32XQCICSR: .attribute 5, "rv32i2p1_xqcicsr0p2"
406 ; RV32XQCIINT: .attribute 5, "rv32i2p1_zca1p0_xqciint0p2"
407 ; RV32XQCILO: .attribute 5, "rv32i2p1_zca1p0_xqcilo0p2"
408 ; RV32XQCILSM: .attribute 5, "rv32i2p1_xqcilsm0p2"
409 ; RV32XQCISLS: .attribute 5, "rv32i2p1_xqcisls0p2"
410 ; RV32ZAAMO: .attribute 5, "rv32i2p1_zaamo1p0"
411 ; RV32ZALRSC: .attribute 5, "rv32i2p1_zalrsc1p0"
412 ; RV32ZCA: .attribute 5, "rv32i2p1_zca1p0"
413 ; RV32ZCB: .attribute 5, "rv32i2p1_zca1p0_zcb1p0"
414 ; RV32ZCD: .attribute 5, "rv32i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcd1p0"
415 ; RV32ZCF: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zca1p0_zcf1p0"
416 ; RV32ZCMP: .attribute 5, "rv32i2p1_zca1p0_zcmp1p0"
417 ; RV32ZCMT: .attribute 5, "rv32i2p1_zicsr2p0_zca1p0_zcmt1p0"
418 ; RV32ZICSR: .attribute 5, "rv32i2p1_zicsr2p0"
419 ; RV32ZIFENCEI: .attribute 5, "rv32i2p1_zifencei2p0"
420 ; RV32ZICNTR: .attribute 5, "rv32i2p1_zicntr2p0_zicsr2p0"
421 ; RV32ZIHPM: .attribute 5, "rv32i2p1_zicsr2p0_zihpm2p0"
422 ; RV32ZFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa1p0"
423 ; RV32ZVBB: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvkb1p0_zvl32b1p0"
424 ; RV32ZVBC: .attribute 5, "rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
425 ; RV32ZVKB: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvl32b1p0"
426 ; RV32ZVKG: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg1p0_zvl32b1p0"
427 ; RV32ZVKN: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
428 ; RV32ZVKNC: .attribute 5, "rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
429 ; RV32ZVKNED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned1p0_zvl32b1p0"
430 ; RV32ZVKNG: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
431 ; RV32ZVKNHA: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha1p0_zvl32b1p0"
432 ; RV32ZVKNHB: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknhb1p0_zvl32b1p0_zvl64b1p0"
433 ; RV32ZVKS: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
434 ; RV32ZVKSC: .attribute 5, "rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
435 ; RV32ZVKSED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed1p0_zvl32b1p0"
436 ; RV32ZVKSG: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
437 ; RV32ZVKSH: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh1p0_zvl32b1p0"
438 ; RV32ZVKT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0"
439 ; RV32ZVFH: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0"
440 ; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0"
441 ; RV32ZIMOP: .attribute 5, "rv32i2p1_zimop1p0"
442 ; RV32ZCMOP: .attribute 5, "rv32i2p1_zca1p0_zcmop1p0"
443 ; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0"
444 ; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
445 ; RV32SMCSRIND: .attribute 5, "rv32i2p1_smcsrind1p0"
446 ; RV32SSCSRIND: .attribute 5, "rv32i2p1_sscsrind1p0"
447 ; RV32SMDBLTRP: .attribute 5, "rv32i2p1_smdbltrp1p0"
448 ; RV32SSDBLTRP: .attribute 5, "rv32i2p1_ssdbltrp1p0"
449 ; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
450 ; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0"
451 ; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
452 ; RV32SMRNMI: .attribute 5, "rv32i2p1_smrnmi1p0"
453 ; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
454 ; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
455 ; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
456 ; RV32ZACAS: .attribute 5, "rv32i2p1_zaamo1p0_zacas1p0"
457 ; RV32ZALASR: .attribute 5, "rv32i2p1_zalasr0p1"
458 ; RV32ZAMA16B: .attribute 5, "rv32i2p1_zama16b1p0"
459 ; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp1p0_zicsr2p0"
460 ; RV32ZABHA: .attribute 5, "rv32i2p1_zaamo1p0_zabha1p0"
461 ; RV32ZVBC32E: .attribute 5, "rv32i2p1_zicsr2p0_zvbc32e0p7_zve32x1p0_zvl32b1p0"
462 ; RV32ZVKGS: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg1p0_zvkgs0p7_zvl32b1p0"
463 ; RV32SSNPM: .attribute 5, "rv32i2p1_ssnpm1p0"
464 ; RV32SMNPM: .attribute 5, "rv32i2p1_smnpm1p0"
465 ; RV32SMMPM: .attribute 5, "rv32i2p1_smmpm1p0"
466 ; RV32SSPM: .attribute 5, "rv32i2p1_sspm1p0"
467 ; RV32SUPM: .attribute 5, "rv32i2p1_supm1p0"
468 ; RV32SMCTR: .attribute 5, "rv32i2p1_smctr1p0_sscsrind1p0"
469 ; RV32SSCTR: .attribute 5, "rv32i2p1_sscsrind1p0_ssctr1p0"
471 ; RV64M: .attribute 5, "rv64i2p1_m2p0_zmmul1p0"
472 ; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
473 ; RV64MZMMUL: .attribute 5, "rv64i2p1_m2p0_zmmul1p0"
474 ; RV64A: .attribute 5, "rv64i2p1_a2p1_zaamo1p0_zalrsc1p0"
475 ; RV64B: .attribute 5, "rv64i2p1_b1p0_zba1p0_zbb1p0_zbs1p0"
476 ; RV64F: .attribute 5, "rv64i2p1_f2p2_zicsr2p0"
477 ; RV64D: .attribute 5, "rv64i2p1_f2p2_d2p2_zicsr2p0"
478 ; RV64C: .attribute 5, "rv64i2p1_c2p0"
479 ; RV64ZIHINTPAUSE: .attribute 5, "rv64i2p1_zihintpause2p0"
480 ; RV64ZIHINTNTL: .attribute 5, "rv64i2p1_zihintntl1p0"
481 ; RV64ZFHMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfhmin1p0"
482 ; RV64ZFH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfh1p0_zfhmin1p0"
483 ; RV64ZBA: .attribute 5, "rv64i2p1_zba1p0"
484 ; RV64ZBB: .attribute 5, "rv64i2p1_zbb1p0"
485 ; RV64ZBC: .attribute 5, "rv64i2p1_zbc1p0"
486 ; RV64ZBS: .attribute 5, "rv64i2p1_zbs1p0"
487 ; RV64V: .attribute 5, "rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
488 ; RV64H: .attribute 5, "rv64i2p1_h1p0"
489 ; RV64COMBINED: .attribute 5, "rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zfhmin1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
490 ; RV64ZBKB: .attribute 5, "rv64i2p1_zbkb1p0"
491 ; RV64ZBKC: .attribute 5, "rv64i2p1_zbkc1p0"
492 ; RV64ZBKX: .attribute 5, "rv64i2p1_zbkx1p0"
493 ; RV64ZKND: .attribute 5, "rv64i2p1_zknd1p0"
494 ; RV64ZKNE: .attribute 5, "rv64i2p1_zkne1p0"
495 ; RV64ZKNH: .attribute 5, "rv64i2p1_zknh1p0"
496 ; RV64ZKSED: .attribute 5, "rv64i2p1_zksed1p0"
497 ; RV64ZKSH: .attribute 5, "rv64i2p1_zksh1p0"
498 ; RV64ZKR: .attribute 5, "rv64i2p1_zkr1p0"
499 ; RV64ZKN: .attribute 5, "rv64i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
500 ; RV64ZKS: .attribute 5, "rv64i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
501 ; RV64ZKT: .attribute 5, "rv64i2p1_zkt1p0"
502 ; RV64ZK: .attribute 5, "rv64i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
503 ; RV64COMBINEINTOZK: .attribute 5, "rv64i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
504 ; RV64COMBINEINTOZKN: .attribute 5, "rv64i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
505 ; RV64COMBINEINTOZKS: .attribute 5, "rv64i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
506 ; RV64ZIC64B: .attribute 5, "rv64i2p1_zic64b1p0"
507 ; RV64ZICBOM: .attribute 5, "rv64i2p1_zicbom1p0"
508 ; RV64ZICBOZ: .attribute 5, "rv64i2p1_zicboz1p0"
509 ; RV64ZA64RS: .attribute 5, "rv64i2p1_za64rs1p0"
510 ; RV64ZA128RS: .attribute 5, "rv64i2p1_za128rs1p0"
511 ; RV64ZAMA16B: .attribute 5, "rv64i2p1_zama16b1p0"
512 ; RV64ZAWRS: .attribute 5, "rv64i2p1_zawrs1p0"
513 ; RV64ZICBOP: .attribute 5, "rv64i2p1_zicbop1p0"
514 ; RV64SHA: .attribute 5, "rv64i2p1_h1p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssstateen1p0"
515 ; RV64SHCOUNTERENW: .attribute 5, "rv64i2p1_shcounterenw1p0"
516 ; RV64SHGATPA: .attribute 5, "rv64i2p1_shgatpa1p0"
517 ; RV64SHVSATPA: .attribute 5, "rv64i2p1_shvsatpa1p0"
518 ; RV64SSCCFG: .attribute 5, "rv64i2p1_ssccfg1p0"
519 ; RV64SSCCPTR: .attribute 5, "rv64i2p1_ssccptr1p0"
520 ; RV64SSCOFPMF: .attribute 5, "rv64i2p1_sscofpmf1p0"
521 ; RV64SSCOUNTERENW: .attribute 5, "rv64i2p1_sscounterenw1p0"
522 ; RV64SMSTATEEN: .attribute 5, "rv64i2p1_smstateen1p0"
523 ; RV64SSSTATEEN: .attribute 5, "rv64i2p1_ssstateen1p0"
524 ; RV64SSSTRICT: .attribute 5, "rv64i2p1_ssstrict1p0"
525 ; RV64SSTC: .attribute 5, "rv64i2p1_sstc1p0"
526 ; RV64SHTVALA: .attribute 5, "rv64i2p1_shtvala1p0"
527 ; RV64SHVSTVALA: .attribute 5, "rv64i2p1_shvstvala1p0"
528 ; RV64SHVSTVECD: .attribute 5, "rv64i2p1_shvstvecd1p0"
529 ; RV64SSTVALA: .attribute 5, "rv64i2p1_sstvala1p0"
530 ; RV64SSTVECD: .attribute 5, "rv64i2p1_sstvecd1p0"
531 ; RV64SSU64XL: .attribute 5, "rv64i2p1_ssu64xl1p0"
532 ; RV64SVADE: .attribute 5, "rv64i2p1_svade1p0"
533 ; RV64SVADU: .attribute 5, "rv64i2p1_svadu1p0"
534 ; RV64SVBARE: .attribute 5, "rv64i2p1_svbare1p0"
535 ; RV64SVNAPOT: .attribute 5, "rv64i2p1_svnapot1p0"
536 ; RV64SVPBMT: .attribute 5, "rv64i2p1_svpbmt1p0"
537 ; RV64SVUKTE: .attribute 5, "rv64i2p1_svukte0p3"
538 ; RV64SVVPTC: .attribute 5, "rv64i2p1_svvptc1p0"
539 ; RV64SVINVAL: .attribute 5, "rv64i2p1_svinval1p0"
540 ; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p1_xventanacondops1p0"
541 ; RV64XSFVFWMACCQQQ: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0_xsfvfwmaccqqq1p0"
542 ; RV64XTHEADBA: .attribute 5, "rv64i2p1_xtheadba1p0"
543 ; RV64XTHEADBB: .attribute 5, "rv64i2p1_xtheadbb1p0"
544 ; RV64XTHEADBS: .attribute 5, "rv64i2p1_xtheadbs1p0"
545 ; RV64XTHEADCMO: .attribute 5, "rv64i2p1_xtheadcmo1p0"
546 ; RV64XTHEADCONDMOV: .attribute 5, "rv64i2p1_xtheadcondmov1p0"
547 ; RV64XTHEADFMEMIDX: .attribute 5, "rv64i2p1_xtheadfmemidx1p0"
548 ; RV64XTHEADMAC: .attribute 5, "rv64i2p1_xtheadmac1p0"
549 ; RV64XTHEADMEMIDX: .attribute 5, "rv64i2p1_xtheadmemidx1p0"
550 ; RV64XTHEADMEMPAIR: .attribute 5, "rv64i2p1_xtheadmempair1p0"
551 ; RV64XTHEADSYNC: .attribute 5, "rv64i2p1_xtheadsync1p0"
552 ; RV64XTHEADVDOT: .attribute 5, "rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0"
553 ; RV64ZTSO: .attribute 5, "rv64i2p1_ztso1p0"
554 ; RV64ZAAMO: .attribute 5, "rv64i2p1_zaamo1p0"
555 ; RV64ZALRSC: .attribute 5, "rv64i2p1_zalrsc1p0"
556 ; RV64ZCA: .attribute 5, "rv64i2p1_zca1p0"
557 ; RV64ZCB: .attribute 5, "rv64i2p1_zca1p0_zcb1p0"
558 ; RV64ZCD: .attribute 5, "rv64i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcd1p0"
559 ; RV64ZCMP: .attribute 5, "rv64i2p1_zca1p0_zcmp1p0"
560 ; RV64ZCMT: .attribute 5, "rv64i2p1_zicsr2p0_zca1p0_zcmt1p0"
561 ; RV64ZICCAMOA: .attribute 5, "rv64i2p1_ziccamoa1p0"
562 ; RV64ZICCIF: .attribute 5, "rv64i2p1_ziccif1p0"
563 ; RV64ZICCLSM: .attribute 5, "rv64i2p1_zicclsm1p0"
564 ; RV64ZICCRSE: .attribute 5, "rv64i2p1_ziccrse1p0"
565 ; RV64ZICSR: .attribute 5, "rv64i2p1_zicsr2p0"
566 ; RV64ZIFENCEI: .attribute 5, "rv64i2p1_zifencei2p0"
567 ; RV64ZICNTR: .attribute 5, "rv64i2p1_zicntr2p0_zicsr2p0"
568 ; RV64ZIHPM: .attribute 5, "rv64i2p1_zicsr2p0_zihpm2p0"
569 ; RV64ZFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfa1p0"
570 ; RV64ZVBB: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvkb1p0_zvl32b1p0"
571 ; RV64ZVBC: .attribute 5, "rv64i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
572 ; RV64ZVKB: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvl32b1p0"
573 ; RV64ZVKG: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkg1p0_zvl32b1p0"
574 ; RV64ZVKN: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
575 ; RV64ZVKNC: .attribute 5, "rv64i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
576 ; RV64ZVKNED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkned1p0_zvl32b1p0"
577 ; RV64ZVKNG: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
578 ; RV64ZVKNHA: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvknha1p0_zvl32b1p0"
579 ; RV64ZVKNHB: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknhb1p0_zvl32b1p0_zvl64b1p0"
580 ; RV64ZVKS: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0"
581 ; RV64ZVKSC: .attribute 5, "rv64i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
582 ; RV64ZVKSED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksed1p0_zvl32b1p0"
583 ; RV64ZVKSG: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl32b1p0"
584 ; RV64ZVKSH: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksh1p0_zvl32b1p0"
585 ; RV64ZVKT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0"
586 ; RV64ZVFH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0"
587 ; RV64ZICOND: .attribute 5, "rv64i2p1_zicond1p0"
588 ; RV64ZIMOP: .attribute 5, "rv64i2p1_zimop1p0"
589 ; RV64ZCMOP: .attribute 5, "rv64i2p1_zca1p0_zcmop1p0"
590 ; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0"
591 ; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
592 ; RV64SMCSRIND: .attribute 5, "rv64i2p1_smcsrind1p0"
593 ; RV64SSCSRIND: .attribute 5, "rv64i2p1_sscsrind1p0"
594 ; RV64SMDBLTRP: .attribute 5, "rv64i2p1_smdbltrp1p0"
595 ; RV64SSDBLTRP: .attribute 5, "rv64i2p1_ssdbltrp1p0"
596 ; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
597 ; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0"
598 ; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
599 ; RV64SMRNMI: .attribute 5, "rv64i2p1_smrnmi1p0"
600 ; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"
601 ; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
602 ; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
603 ; RV64ZACAS: .attribute 5, "rv64i2p1_zaamo1p0_zacas1p0"
604 ; RV64ZALASR: .attribute 5, "rv64i2p1_zalasr0p1"
605 ; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp1p0_zicsr2p0"
606 ; RV64ZABHA: .attribute 5, "rv64i2p1_zaamo1p0_zabha1p0"
607 ; RV64ZVBC32E: .attribute 5, "rv64i2p1_zicsr2p0_zvbc32e0p7_zve32x1p0_zvl32b1p0"
608 ; RV64ZVKGS: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkg1p0_zvkgs0p7_zvl32b1p0"
609 ; RV64SSNPM: .attribute 5, "rv64i2p1_ssnpm1p0"
610 ; RV64SMNPM: .attribute 5, "rv64i2p1_smnpm1p0"
611 ; RV64SMMPM: .attribute 5, "rv64i2p1_smmpm1p0"
612 ; RV64SSPM: .attribute 5, "rv64i2p1_sspm1p0"
613 ; RV64SUPM: .attribute 5, "rv64i2p1_supm1p0"
614 ; RV64SMCTR: .attribute 5, "rv64i2p1_smctr1p0_sscsrind1p0"
615 ; RV64SSCTR: .attribute 5, "rv64i2p1_sscsrind1p0_ssctr1p0"
616 ; RV64SDEXT: .attribute 5, "rv64i2p1_sdext1p0"
617 ; RV64SDTRIG: .attribute 5, "rv64i2p1_sdtrig1p0"
619 ; RVI20U32: .attribute 5, "rv32i2p1"
620 ; RVI20U64: .attribute 5, "rv64i2p1"
621 ; RVA20U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zmmul1p0_za128rs1p0_zaamo1p0_zalrsc1p0"
622 ; RVA20S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zmmul1p0_za128rs1p0_zaamo1p0_zalrsc1p0_ssccptr1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0"
623 ; RVA22U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0"
624 ; RVA22S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscounterenw1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0_svinval1p0_svpbmt1p0"
625 ; RVA23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_supm1p0"
626 ; RVA23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm1p0_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"
627 ; RVB23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0"
628 ; RVB23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"
629 ; RVM23U32: .attribute 5, "rv32i2p1_m2p0_b1p0_zicbop1p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zimop1p0_zmmul1p0_zca1p0_zcb1p0_zce1p0_zcmop1p0_zcmp1p0_zcmt1p0_zba1p0_zbb1p0_zbs1p0"
639 ; A6S: .attribute 14, 2
640 ; A6C: .attribute 14, 1