[RISCV] Renaming muladdi to muliadd as per v0.5 spec. (#124237)

muliadd is more relevant to the operation performed, i.e. multiply by
immediate.

The latest spec can be found at:
https://github.com/

[RISCV] Renaming muladdi to muliadd as per v0.5 spec. (#124237)

muliadd is more relevant to the operation performed, i.e. multiply by
immediate.

The latest spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

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[RISCV] Add Qualcomm uC Xqcilo (Large Offset Load Store) extension (#123881)

This extension adds eight 48 bit load store instructions.

The current spec can be found at:
https://github.com/quic/r

[RISCV] Add Qualcomm uC Xqcilo (Large Offset Load Store) extension (#123881)

This extension adds eight 48 bit load store instructions.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>

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[RISCV] Add Qualcomm uC Xqciint (Interrupts) extension (#122256)

This extension adds eleven instructions to accelerate interrupt
servicing.

The current spec can be found at:
https://github.com/

[RISCV] Add Qualcomm uC Xqciint (Interrupts) extension (#122256)

This extension adds eleven instructions to accelerate interrupt
servicing.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>

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[RISCV] Add Qualcomm uC Xqcicm (Conditional Move) extension (#121752)

The Qualcomm uC Xqcicm extension adds 13 conditional move instructions.

The current spec can be found at:
https://github.co

[RISCV] Add Qualcomm uC Xqcicm (Conditional Move) extension (#121752)

The Qualcomm uC Xqcicm extension adds 13 conditional move instructions.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>

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[RISCV] Add support of Sdext,Sdtrig extentions (#120936)

`Sdext` and `Sdtrig` are RISC-V extensions related to debugging.

The full specification can be found at

https://github.com/riscv/riscv-

[RISCV] Add support of Sdext,Sdtrig extentions (#120936)

`Sdext` and `Sdtrig` are RISC-V extensions related to debugging.

The full specification can be found at

https://github.com/riscv/riscv-debug-spec/releases/download/1.0.0-rc4/riscv-debug-specification.pdf

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[RISCV] Add Qualcomm uC Xqcicli (Conditional Load Immediate) extension (#121292)

This extension adds 12 instructions that conditionally load an immediate
value.

The current spec can be found at:

[RISCV] Add Qualcomm uC Xqcicli (Conditional Load Immediate) extension (#121292)

This extension adds 12 instructions that conditionally load an immediate
value.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

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[RISCV] Add Qualcomm uC Xqciac (Load-Store Adress calculation) extension (#121037)

This extension adds 3 instructions that perform load-store address
calculation.

The current spec can be found a

[RISCV] Add Qualcomm uC Xqciac (Load-Store Adress calculation) extension (#121037)

This extension adds 3 instructions that perform load-store address
calculation.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>

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[RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (#119823)

This extension adds 6 instructions that can do multi-word load/store.

The current spec can be found at:
https://github.c

[RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (#119823)

This extension adds 6 instructions that can do multi-word load/store.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

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[RISCV] Add Qualcomm uC Xqcics(Conditional Select) extension (#119504)

The Qualcomm uC Xqcics extension adds 8 conditional select instructions.

The current spec can be found at:
https://github.c

[RISCV] Add Qualcomm uC Xqcics(Conditional Select) extension (#119504)

The Qualcomm uC Xqcics extension adds 8 conditional select instructions.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>

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[RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (#118113)

This extension adds 11 instructions that perform integer arithmetic.

The current spec can be found at:
https://github.com/quic/risc

[RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (#118113)

This extension adds 11 instructions that perform integer arithmetic.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

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[RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store) extension (#117987)

This extension adds 8 load/store instructions with a scaled index
addressing mode.

The current spec can be found at:
http

[RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store) extension (#117987)

This extension adds 8 load/store instructions with a scaled index
addressing mode.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

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[RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169)

The Qualcomm uC Xqcicsr extension adds 2 instructions that can read and
write CSRs.

The current spec can be found at:
https://github.co

[RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169)

The Qualcomm uC Xqcicsr extension adds 2 instructions that can read and
write CSRs.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

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[RISCV] Support `svukte` extension (#115657)

This is the extension for "Address-Independent Latency of User-Mode
Faults to Supervisor Addresses".
Spec: https://github.com/riscv/riscv-isa-manual/pu

[RISCV] Support `svukte` extension (#115657)

This is the extension for "Address-Independent Latency of User-Mode
Faults to Supervisor Addresses".
Spec: https://github.com/riscv/riscv-isa-manual/pull/1564,
https://lf-riscv.atlassian.net/browse/RVS-2977
The spec states that the `svukte` depends on `sv39`, but we don't have
`sv39` yet, so I didn't add it to the implied list.

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[RISCV] Make A implies Zaamo and Zalrsc (#116907)

Ref:
https://github.com/riscv/riscv-isa-manual/blob/main/src/a-st-ext.adoc.

[RISCV] Remove +a from the attribute test for zacas and zabha. NFC.

zacas and zabha don't require the 'a' or 'zaamo' extension after
https://github.com/llvm/llvm-project/pull/115694.

[RISCV] Zabha/Zacas implies Zaamo (#115694)

The Zabha/Zacas extension depends upon the Zaamo extension.
Ref: https://github.com/riscv/riscv-isa-manual/blob/main/src/zacas.adoc
https://github.com/

[RISCV] Zabha/Zacas implies Zaamo (#115694)

The Zabha/Zacas extension depends upon the Zaamo extension.
Ref: https://github.com/riscv/riscv-isa-manual/blob/main/src/zacas.adoc
https://github.com/riscv/riscv-isa-manual/blob/main/src/zabha.adoc.

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[RISCV] Use the 'B' extension in RISC-V profile definitions (#113942)

RVA22 has retroactively been defined as including 'B' (as it's a
shorthand for Zba+Zbb+Zbs, which were previously explicitly en

[RISCV] Use the 'B' extension in RISC-V profile definitions (#113942)

RVA22 has retroactively been defined as including 'B' (as it's a
shorthand for Zba+Zbb+Zbs, which were previously explicitly enumerated)
and RV{A,B,M}23 are defined featuring B. We don't currently infer B
whenever Zba+Zbb+Zbs are present due to concerns about compatibility
with external assemblers such as gas.

We don't believe that adding B to RVA22 will cause issues for users who
(for instance) build with clang and assemble with binutils as looking at
the binutils commit history:
zic64b support was only committed in
25f05199bb7e35820c23e802424484accb7936b1 in July 2024
B support was committed in c144f638337944101131d9fe6de4ab908f6d4c2d in
May 2024

So given we emit zic64b anyway (as it has always been in the RVA22
spec), no binutils that would have previously successfully assembled our
rva22u64 output should fail due to the addition of 'B'.

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[RISCV] Add Smdbltrp and Ssdbltrp extension (#111837)

Smdbltrp and Ssdbltrp supports are added in this PR.
Specification link(Smdbltrp) :
[https://github.com/riscv/riscv-isa-manual/blob/main/src/s

[RISCV] Add Smdbltrp and Ssdbltrp extension (#111837)

Smdbltrp and Ssdbltrp supports are added in this PR.
Specification link(Smdbltrp) :
[https://github.com/riscv/riscv-isa-manual/blob/main/src/smdbltrp.adoc](url)
Specification link(Ssdbltrp) :
[https://github.com/riscv/riscv-isa-manual/blob/main/src/ssdbltrp.adoc](url)

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[RISCV] Mark RVB23U64 and RVB23S64 as non-experimental (#113918)

The specification was recently ratified

<https://github.com/riscv/riscv-profiles/blob/main/src/rvb23-profile.adoc>.

[RISCV] Mark the RVA23S64 and RVA23U64 profiles as non-experimental (#113826)

All of the extensions used by these profile are themselves
non-experimental, and RVA23 was just ratified

<https://ri

[RISCV] Mark the RVA23S64 and RVA23U64 profiles as non-experimental (#113826)

All of the extensions used by these profile are themselves
non-experimental, and RVA23 was just ratified

<https://riscv.org/announcements/2024/10/risc-v-announces-ratification-of-the-rva23-profile-standard/>.

<https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc>

We lack a way of expressing `Ss1p13` (supervisor architecture 1.13), but
this is a problem we have for RVA22 (Ss1p12) and RVA20 (Ss1p11) so I
don't feel it's a blocker.

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[RISCV]Add svvptc extension (#113882)

[RISCV] Use Sha extension in RVA23S64 profile (#113823)

In the ratified version of the RVA23S64 definition, the Sha extension is
now used to group together the set of hypervisor related extensions.

[RISCV] Use Sha extension in RVA23S64 profile (#113823)

In the ratified version of the RVA23S64 definition, the Sha extension is
now used to group together the set of hypervisor related extensions.

<https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc>

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[RISCV] Add the Sha extension (#113820)

This was introduced in the now-ratified RVA23 profile (and also added to
the RVA22 text) as a simple way of referring to H plus the set of
supervisor extens

[RISCV] Add the Sha extension (#113820)

This was introduced in the now-ratified RVA23 profile (and also added to
the RVA22 text) as a simple way of referring to H plus the set of
supervisor extensions required by RVA23.
https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc

This patch simply defines the extension. The next patch will adjust the
RVA23 profile to use it, and at that point I think we will be ready to
mark RVA23 as non-experimental.

Note that I haven't made it so if you enable all extensions that
constitute Sha, Sha is implied. Per #76893 (adding 'B'), the concern is
making this implication might break older external assemblers. Perhaps
this is less of a concern given the relative frequency of
`-march=${foo}_zba_zbb_zbs` vs the collection of H extensions. If we did
want to add that implication, we'd probably want to add it in a separate
patch so it can be easily reverted if found to cause problems.

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[RISCV] Add Supm extension to RVA23 profiles (#113619)

This is mandatory for both RVA23U64 and RVA23S64 in the ratified version
of the specification

<https://github.com/riscv/riscv-profiles/blob

[RISCV] Add Supm extension to RVA23 profiles (#113619)

This is mandatory for both RVA23U64 and RVA23S64 in the ratified version
of the specification

<https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc>.

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[RISCV] Mark pointer masking extensions as non-experimental (#113618)

These extensions were ratified very recently.

<https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154732/Ratified+Extens

[RISCV] Mark pointer masking extensions as non-experimental (#113618)

These extensions were ratified very recently.

<https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154732/Ratified+Extensions>

I've ensured we have definitions for all extensions in the document
<https://drive.google.com/file/d/159QffOTbi3EEbdkKndYRZ2c46D25ZLmO/view?usp=drive_link>.
There are no additional CSRs.

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