Lines Matching defs:Intf

508   for (const LiveInterval *Intf : Intfs) {
510     if (!VRM->hasPhys(Intf->reg()))
513     Matrix->unassign(*Intf);
514     assert((ExtraInfo->getCascade(Intf->reg()) < Cascade ||
515             VirtReg.isSpillable() < Intf->isSpillable()) &&
517     ExtraInfo->setCascade(Intf->reg(), Cascade);
519     NewVRegs.push_back(Intf->reg());
604 bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf,
616     Intf.moveToBlock(BC.Number);
624     if (!Intf.hasInterference())
632       if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number)) {
635       } else if (Intf.first() < BI.FirstInstr) {
638       } else if (Intf.first() < BI.LastInstr) {
652       if (Intf.last() >= SA->getLastSplitPoint(BC.Number)) {
655       } else if (Intf.last() > BI.LastInstr) {
658       } else if (Intf.last() > BI.FirstInstr) {
677 bool RAGreedy::addThroughConstraints(InterferenceCache::Cursor Intf,
685     Intf.moveToBlock(Number);
687     if (!Intf.hasInterference()) {
708     if (Intf.first() <= Indexes->getMBBStartIdx(Number))
714     if (Intf.last() >= SA->getLastSplitPoint(Number))
769       if (!addThroughConstraints(Cand.Intf, NewBlocks))
823   // The static split cost will be zero since Cand.Intf reports no interference.
825   if (!addSplitConstraints(Cand.Intf, Cost)) {
883     Cand.Intf.moveToBlock(BC.Number);
900       Cand.Intf.moveToBlock(Number);
901       if (Cand.Intf.hasInterference()) {
951         Cand.Intf.moveToBlock(Number);
952         IntfIn = Cand.Intf.first();
960         Cand.Intf.moveToBlock(Number);
961         IntfOut = Cand.Intf.last();
999         Cand.Intf.moveToBlock(Number);
1000         IntfIn = Cand.Intf.first();
1007         Cand.Intf.moveToBlock(Number);
1008         IntfOut = Cand.Intf.last();
1129   if (!addSplitConstraints(Cand.Intf, Cost)) {
1850 /// Return true if the existing assignment of \p Intf overlaps, but is not the
1855                                          const LiveInterval &Intf) {
1856   MCRegister AssignedReg = VRM.getPhys(Intf.reg());
1886     for (const LiveInterval *Intf : reverse(Q.interferingVRegs())) {
1887       // If Intf is done and sits on the same register class as VirtReg, it
1891       // If VirtReg has tied defs and Intf doesn't, then
1898       if (((ExtraInfo->getStage(*Intf) == RS_Done &&
1899             MRI->getRegClass(Intf->reg()) == CurRC &&
1900             !assignedRegPartiallyOverlaps(*TRI, *VRM, PhysReg, *Intf)) &&
1902              !hasTiedDef(MRI, Intf->reg()))) ||
1903           FixedRegisters.count(Intf->reg())) {
1908       RecoloringCandidates.insert(Intf);