Lines Matching refs:Def
458 /// Track Def -> Use info used for rewriting copies.
532 MachineInstr &rewriteSource(MachineInstr &CopyLike, RegSubRegPair Def,
706 const MachineInstr *Def = nullptr;
708 /// The index of the definition in Def.
761 Def = MRI.getVRegDef(Reg);
1006 /// retrieve all Def -> Use along the way up to the next source. Any found
1046 // Insert the Def -> Use entry for the recently found source.
1138 /// Given a \p Def.Reg and Def.SubReg pair, use \p RewriteMap to find
1140 /// multiple sources for a given \p Def are found along the way, we found a
1146 RegSubRegPair Def,
1149 RegSubRegPair LookupSrc(Def.Reg, Def.SubReg);
1266 /// Rewrite the source found through \p Def, by using the \p RewriteMap
1272 RegSubRegPair Def,
1274 assert(!Def.Reg.isPhysical() && "We do not rewrite physical registers");
1277 RegSubRegPair NewSrc = getNewSource(MRI, TII, Def, RewriteMap);
1280 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg);
1288 if (Def.SubReg) {
1289 NewCopy->getOperand(0).setSubReg(Def.SubReg);
1296 MRI->replaceRegWith(Def.Reg, NewVReg);
1327 RegSubRegPair Def;
1329 while (CpyRewriter.getNextRewritableSource(Src, Def)) {
1332 if (Def.Reg.isPhysical())
1337 if (!findNextSource(Def, RewriteMap))
1340 RewritePairs.push_back(Def);
1344 for (const RegSubRegPair &Def : RewritePairs) {
1346 MachineInstr &NewCopy = rewriteSource(MI, Def, RewriteMap);
1744 const auto &Def = NAPhysToVirtMIs.find(Reg);
1745 if (Def != NAPhysToVirtMIs.end()) {
1750 NAPhysToVirtMIs.erase(Def);
1756 Register Def = RegMI.first;
1757 if (MachineOperand::clobbersPhysReg(RegMask, Def)) {
1760 NAPhysToVirtMIs.erase(Def);
1894 assert(Def->isCopy() && "Invalid definition");
1895 // Copy instruction are supposed to be: Def = Src.
1899 assert(Def->getNumOperands() - Def->getNumImplicitOperands() == 2 &&
1901 assert(!Def->hasImplicitDef() && "Only implicit uses are allowed");
1903 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
1908 const MachineOperand &Src = Def->getOperand(1);
1915 assert(Def->isBitcast() && "Invalid definition");
1918 if (Def->mayRaiseFPException() || Def->hasUnmodeledSideEffects())
1922 if (Def->getDesc().getNumDefs() != 1)
1924 const MachineOperand DefOp = Def->getOperand(DefIdx);
1930 unsigned SrcIdx = Def->getNumOperands();
1933 const MachineOperand &MO = Def->getOperand(OpIdx);
1946 // In some rare case, Def has no input, SrcIdx is out of bound,
1948 if (SrcIdx >= Def->getNumOperands())
1958 const MachineOperand &Src = Def->getOperand(SrcIdx);
1965 assert((Def->isRegSequence() || Def->isRegSequenceLike()) &&
1968 if (Def->getOperand(DefIdx).getSubReg())
1970 // The case we are checking is Def.<subreg> = REG_SEQUENCE.
1974 // Def.sub0 =
1975 // Def.sub1 =
1976 // is a valid SSA representation for Def.sub0 and Def.sub1, but not for
1977 // Def. Thus, it must not be generated.
1979 // Def.sub0 (i.e, not defining the other subregs) and we would
1986 if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs))
1990 // Def = REG_SEQUENCE v0, sub0, v1, sub1, ...
2004 assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) &&
2007 if (Def->getOperand(DefIdx).getSubReg())
2015 if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg))
2019 // Def = INSERT_SUBREG v0, v1, sub1
2031 const MachineOperand &MODef = Def->getOperand(DefIdx);
2032 // If the result register (Def) and the base register (v0) do not
2047 // we used for Def.
2052 assert((Def->isExtractSubreg() || Def->isExtractSubregLike()) &&
2055 // Def = EXTRACT_SUBREG v0, sub0
2063 if (!TII->getExtractSubregInputs(*Def, DefIdx, ExtractSubregInputReg))
2076 assert(Def->isSubregToReg() && "Invalid definition");
2078 // Def = SUBREG_TO_REG Imm, v0, sub0
2084 if (DefSubReg != Def->getOperand(3).getImm())
2088 if (Def->getOperand(2).getSubReg())
2091 return ValueTrackerResult(Def->getOperand(2).getReg(),
2092 Def->getOperand(3).getImm());
2097 assert(Def->isPHI() && "Invalid definition");
2102 if (Def->getOperand(0).getSubReg() != DefSubReg)
2106 for (unsigned i = 1, e = Def->getNumOperands(); i < e; i += 2) {
2107 const MachineOperand &MO = Def->getOperand(i);
2120 assert(Def && "This method needs a valid definition");
2122 assert(((Def->getOperand(DefIdx).isDef() &&
2123 (DefIdx < Def->getDesc().getNumDefs() ||
2124 Def->getDesc().isVariadic())) ||
2125 Def->getOperand(DefIdx).isImplicit()) &&
2127 if (Def->isCopy())
2129 if (Def->isBitcast())
2135 if (Def->isRegSequence() || Def->isRegSequenceLike())
2137 if (Def->isInsertSubreg() || Def->isInsertSubregLike())
2139 if (Def->isExtractSubreg() || Def->isExtractSubregLike())
2141 if (Def->isSubregToReg())
2143 if (Def->isPHI())
2151 if (!Def)
2164 Res.setInst(Def);
2171 Def = DI->getParent();
2175 Def = nullptr;
2183 Def = nullptr;