PeepholeOpt: Remove check for subreg index on a def operand (#123943)

This is looking at operand 0 of a REG_SEQUENCE, which can never
have a subregister index.

PeepholeOpt: Stop allocating tiny helper classes (NFC) (#123936)

This was allocating tiny helper classes for every instruction
visited. We can just dispatch over the cases in the visitor
function in

PeepholeOpt: Stop allocating tiny helper classes (NFC) (#123936)

This was allocating tiny helper classes for every instruction
visited. We can just dispatch over the cases in the visitor
function instead.

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PeepholeOpt: Remove null TargetRegisterInfo check (#123933)

This cannot happen. Also simplify the LaneBitmask check from !none
to any.

PeepholeOpt: Remove unnecessary check for null TargetInstrInfo (#123929)

This can never happen.

[aarch64][win] Update Called Globals info when updating Call Site info (#122762)

Fixes the "use after poison" issue introduced by #121516 (see
<https://github.com/llvm/llvm-project/pull/121516#issue

[aarch64][win] Update Called Globals info when updating Call Site info (#122762)

Fixes the "use after poison" issue introduced by #121516 (see
<https://github.com/llvm/llvm-project/pull/121516#issuecomment-2585912395>).

The root cause of this issue is that #121516 introduced "Called Global"
information for call instructions modeling how "Call Site" info is
stored in the machine function, HOWEVER it didn't copy the
copy/move/erase operations for call site information.

The fix is to rename and update the existing copy/move/erase functions
so they also take care of Called Global info.

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[CodeGen][NewPM] Port PeepholeOptimizer to NPM (#116326)

With this, all machine SSA optimization passes are available in the new codegen pipeline.

[NFC] Clang format PeepholeOptimizer (#116325)

[CodeGen][NewPM] Port `machine-loops` to new pass manager (#97793)

- Add `MachineLoopAnalysis`.
- Add `MachineLoopPrinterPass`.
- Convert to `MachineLoopInfoWrapperPass` in legacy pass manager.

[CodeGen] Use range-based for loops (NFC) (#96777)

[CodeGen][NewPM] Split `MachineDominatorTree` into a concrete analysis result (#94571)

Prepare for new pass manager version of `MachineDominatorTreeAnalysis`.
We may need a machine dominator tree v

[CodeGen][NewPM] Split `MachineDominatorTree` into a concrete analysis result (#94571)

Prepare for new pass manager version of `MachineDominatorTreeAnalysis`.
We may need a machine dominator tree version of `DomTreeUpdater` to
handle `SplitCriticalEdge` in some CodeGen passes.

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[CodeGen] Make the parameter TRI required in some functions. (#85968)

Fixes #82659

There are some functions, such as `findRegisterDefOperandIdx` and `findRegisterDefOperand`, that have too many

[CodeGen] Make the parameter TRI required in some functions. (#85968)

Fixes #82659

There are some functions, such as `findRegisterDefOperandIdx` and `findRegisterDefOperand`, that have too many default parameters. As a result, we have encountered some issues due to the lack of TRI parameters, as shown in issue #82411.

Following @RKSimon 's suggestion, this patch refactors 9 functions, including `{reads, kills, defines, modifies}Register`, `registerDefIsDead`, and `findRegister{UseOperandIdx, UseOperand, DefOperandIdx, DefOperand}`, adjusting the order of the TRI parameter and making it required. In addition, all the places that call these functions have also been updated correctly to ensure no additional impact.

After this, the caller of these functions should explicitly know whether to pass the `TargetRegisterInfo` or just a `nullptr`.

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[NFC] Rename TargetInstrInfo::FoldImmediate to TargetInstrInfo::foldImmediate and simplify implementation for X86

[X86, Peephole] Enable FoldImmediate for X86

Enable FoldImmediate for X86 by implementing X86InstrInfo::FoldImmediate.

Also enhanced peephole by deleting identical instructions after FoldImmediate.

[X86, Peephole] Enable FoldImmediate for X86

Enable FoldImmediate for X86 by implementing X86InstrInfo::FoldImmediate.

Also enhanced peephole by deleting identical instructions after FoldImmediate.

Differential Revision: https://reviews.llvm.org/D151848

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Revert 24633ea and 760e7d0 "Enable FoldImmediate for X86"

This reverts commits 24633eac38d46cd4b253ba53258165ee08d886cd
and 760e7d00d142ba85fcf48c00e0acc14a355da7c3.

I have confirmed that these com

Revert 24633ea and 760e7d0 "Enable FoldImmediate for X86"

This reverts commits 24633eac38d46cd4b253ba53258165ee08d886cd
and 760e7d00d142ba85fcf48c00e0acc14a355da7c3.

I have confirmed that these commits are introducing a new crash in the
peephole optimizer. I have minimized a test case, which you can find
below.

```llvmir
; ModuleID = 'bugpoint-reduced-simplified.bc'
source_filename = "/mnt/big/modular/Kernels/mojo/Mogg/MOGG.mojo"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

declare dso_local void @foo({ { ptr, [4 x i64], [4 x i64], i1 }, { ptr, [4 x i64], [4 x i64], i1 } }, { ptr }, { ptr, i64, i8 })

define dso_local void @bad_fn(ptr %0, ptr %1, ptr %2) {
%4 = load i64, ptr null, align 8
%5 = insertvalue [4 x i64] poison, i64 12, 1
%6 = insertvalue [4 x i64] %5, i64 poison, 2
%7 = insertvalue [4 x i64] %6, i64 poison, 3
%8 = insertvalue { ptr, [4 x i64], [4 x i64], i1 } poison, [4 x i64] %7, 1
%9 = insertvalue { ptr, [4 x i64], [4 x i64], i1 } %8, [4 x i64] poison, 2
%10 = insertvalue { ptr, [4 x i64], [4 x i64], i1 } %9, i1 poison, 3
%11 = icmp ne i64 %4, 1
%12 = or i1 false, %11
%13 = select i1 %12, i64 %4, i64 0
%14 = zext i1 %12 to i64
%15 = insertvalue [4 x i64] poison, i64 12, 1
%16 = insertvalue [4 x i64] %15, i64 poison, 2
%17 = insertvalue [4 x i64] %16, i64 %13, 3
%18 = insertvalue [4 x i64] poison, i64 %14, 3
%19 = icmp eq i64 0, 0
%20 = icmp eq i64 0, 0
%21 = icmp eq i64 %13, 0
%22 = and i1 %20, %19
%23 = select i1 %22, i1 %21, i1 false
%24 = select i1 %23, i1 %12, i1 false
%25 = insertvalue { ptr, [4 x i64], [4 x i64], i1 } poison, [4 x i64] %17, 1
%26 = insertvalue { ptr, [4 x i64], [4 x i64], i1 } %25, [4 x i64] %18, 2
%27 = insertvalue { ptr, [4 x i64], [4 x i64], i1 } %26, i1 %24, 3
%28 = insertvalue { { ptr, [4 x i64], [4 x i64], i1 }, { ptr, [4 x i64], [4 x i64], i1 } } undef, { ptr, [4 x i64], [4 x i64], i1 } %10, 0
%29 = insertvalue { { ptr, [4 x i64], [4 x i64], i1 }, { ptr, [4 x i64], [4 x i64], i1 } } %28, { ptr, [4 x i64], [4 x i64], i1 } %27, 1
br label %31

30: ; preds = %3
br label %softmax_pass

31: ; preds = %31
%exitcond.not.i = icmp eq i64 poison, 3
br i1 %exitcond.not.i, label %37, label %31

32: ; preds = %31
br i1 poison, label %34, label %33

33: ; preds = %32
br label %34

34: ; preds = %33, %32
br i1 poison, label %35, label %36

35: ; preds = %34
br label %softmax_pass

36: ; preds = %34
br i1 poison, label %37, label %.critedge.i

37: ; preds = %36
br i1 poison, label %38, label %.critedge.i

38: ; preds = %37
br i1 poison, label %40, label %39

39: ; preds = %38
br label %40

40: ; preds = %39, %38
br i1 poison, label %.lr.ph28.i, label %._crit_edge.i

.lr.ph28.i: ; preds = %40
br label %41

41: ; preds = %51, %.lr.ph28.i
br i1 poison, label %.thread, label %42

42: ; preds = %41
br i1 poison, label %43, label %44

43: ; preds = %42
br label %45

44: ; preds = %42
br label %45

45: ; preds = %44, %43
br i1 poison, label %46, label %.thread

46: ; preds = %45
br label %47

.thread: ; preds = %45, %41
br label %47

47: ; preds = %.thread, %46
br i1 poison, label %51, label %48

48: ; preds = %47
br i1 poison, label %49, label %50

49: ; preds = %48
br label %51

50: ; preds = %48
br label %51

51: ; preds = %50, %49, %47
call void @foo({ { ptr, [4 x i64], [4 x i64], i1 }, { ptr, [4 x i64], [4 x i64], i1 } } %29, { ptr } poison, { ptr, i64, i8 } poison)
br i1 poison, label %._crit_edge.i, label %41

._crit_edge.i: ; preds = %51, %40
br label %softmax_pass

.critedge.i: ; preds = %37, %36
br i1 poison, label %.lr.ph.i, label %softmax_pass

.lr.ph.i: ; preds = %.lr.ph.i, %.critedge.i
store { ptr, [4 x i64], [4 x i64], i1 } %10, ptr poison, align 8
br i1 poison, label %.lr.ph.i, label %softmax_pass

softmax_pass: ; preds = %.lr.ph.i, %.critedge.i, %._crit_edge.i, %35, %30
ret void
}
```

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[Peephole] Check instructions from CopyMIs are still COPY (#69511)

Function foldRedundantCopy records COPY instructions in CopyMIs and uses
it later. But other optimizations may delete or modify it

[Peephole] Check instructions from CopyMIs are still COPY (#69511)

Function foldRedundantCopy records COPY instructions in CopyMIs and uses
it later. But other optimizations may delete or modify it. So before
using it we should check if the extracted instruction is existing and
still a COPY instruction.

show more ...

[X86, Peephole] Enable FoldImmediate for X86

Enable FoldImmediate for X86 by implementing X86InstrInfo::FoldImmediate.

Also enhanced peephole by deleting identical instructions after FoldImmediate.

[X86, Peephole] Enable FoldImmediate for X86

Enable FoldImmediate for X86 by implementing X86InstrInfo::FoldImmediate.

Also enhanced peephole by deleting identical instructions after FoldImmediate.

Differential Revision: https://reviews.llvm.org/D151848

show more ...

Fix uninitialized pointer members in CodeGen

This change initializes the members TSI, LI, DT, PSI, and ORE pointer feilds of the SelectOptimize class to nullptr.

Reviewed By: LuoYuanke

Differentia

Fix uninitialized pointer members in CodeGen

This change initializes the members TSI, LI, DT, PSI, and ORE pointer feilds of the SelectOptimize class to nullptr.

Reviewed By: LuoYuanke

Differential Revision: https://reviews.llvm.org/D148303

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[CodeGen] Remove uses of Register::isPhysicalRegister/isVirtualRegister. NFC

Use isPhysical/isVirtual methods.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D141715

[CodeGen] llvm::Optional => std::optional

Teach PeepholeOpt to eliminate redundant copy from constant physreg (e.g VLENB on RISCV)

The existing redundant copy elimination required a virtual register source, but the same logic works for any

Teach PeepholeOpt to eliminate redundant copy from constant physreg (e.g VLENB on RISCV)

The existing redundant copy elimination required a virtual register source, but the same logic works for any physreg where we don't have to worry about clobbers. On RISCV, this helps eliminate redundant CSR reads from VLENB.

Differential Revision: https://reviews.llvm.org/D125564

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[NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated comments

Cleanup codegen includes

This is a (fixed) recommit of https://reviews.llvm.org/D121169

after: 1061034926
before: 1063332844

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-in

Cleanup codegen includes

This is a (fixed) recommit of https://reviews.llvm.org/D121169

after: 1061034926
before: 1063332844

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D121681

show more ...

Revert "Cleanup codegen includes"

This reverts commit 7f230feeeac8a67b335f52bd2e900a05c6098f20.
Breaks CodeGenCUDA/link-device-bitcode.cu in check-clang,
and many LLVM tests, see comments on https:/

Revert "Cleanup codegen includes"

This reverts commit 7f230feeeac8a67b335f52bd2e900a05c6098f20.
Breaks CodeGenCUDA/link-device-bitcode.cu in check-clang,
and many LLVM tests, see comments on https://reviews.llvm.org/D121169

show more ...

Cleanup codegen includes

after: 1061034926
before: 1063332844

Differential Revision: https://reviews.llvm.org/D121169

[CodeGen] Use = default (NFC)

Identified with modernize-use-equals-default