| 0edc184e | 23-Aug-2024 |
Alexey Marchuk <alexeymar@nvidia.com> |
accel/mlx5: Support mkey registration
Register scatter/gather mkey if accel_mlx5 driver is enabled and a copy task with RDMA memory domain as a destination is set. The UMR can be sent in NVMF capsul
accel/mlx5: Support mkey registration
Register scatter/gather mkey if accel_mlx5 driver is enabled and a copy task with RDMA memory domain as a destination is set. The UMR can be sent in NVMF capsule to represent scattered memory as virtually contiguous.
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: I92e8c417bbf8c4018ac77e7fc074ac7ae9a68b55 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/24708 Community-CI: Mellanox Build Bot Reviewed-by: Ben Walker <ben@nvidia.com> Community-CI: Community CI Samsung <spdk.community.ci.samsung@gmail.com> Reviewed-by: Shuhei Matsumoto <smatsumoto@nvidia.com> Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
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| 0ea9ac02 | 22-Aug-2024 |
Alexey Marchuk <alexeymar@nvidia.com> |
accel/mlx5: Create pool of UMRs
Create a pool of UMR without offloads capability/BSF per device.
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: Ia285c9c692f97db5e562d4e4ea1f49a0787
accel/mlx5: Create pool of UMRs
Create a pool of UMR without offloads capability/BSF per device.
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: Ia285c9c692f97db5e562d4e4ea1f49a07870f28c Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/24707 Reviewed-by: Shuhei Matsumoto <smatsumoto@nvidia.com> Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Community-CI: Mellanox Build Bot Reviewed-by: Ben Walker <ben@nvidia.com> Community-CI: Community CI Samsung <spdk.community.ci.samsung@gmail.com>
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| e2dfdf06 | 18-Jul-2024 |
Alexey Marchuk <alexeymar@nvidia.com> |
accel/mlx5: Register post_poller handler
Register the handler when handling a new request. Update doorbells in the handler
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: I9e3e2e0f6
accel/mlx5: Register post_poller handler
Register the handler when handling a new request. Update doorbells in the handler
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: I9e3e2e0f6f742b55203bb433c05c73c8885bec32 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/24705 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Shuhei Matsumoto <smatsumoto@nvidia.com> Community-CI: Broadcom CI <spdk-ci.pdl@broadcom.com> Reviewed-by: Konrad Sztyber <konrad.sztyber@intel.com> Community-CI: Community CI Samsung <spdk.community.ci.samsung@gmail.com> Community-CI: Mellanox Build Bot Reviewed-by: Jim Harris <jim.harris@nvidia.com>
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| 3c800111 | 18-Jul-2024 |
Alexey Marchuk <alexeymar@nvidia.com> |
accel/mlx5: More precise condition to update DB
The number of outstanding WRs isn't a precise condition to update doorbells since we may have WRs already submitted to HW but not completed and we may
accel/mlx5: More precise condition to update DB
The number of outstanding WRs isn't a precise condition to update doorbells since we may have WRs already submitted to HW but not completed and we may update do unnecessary DB update. Use a dedicated flag to check if DB update is required
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: I941a0724902751cbbebea9f2cc94e8d5247b1182 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/24704 Community-CI: Mellanox Build Bot Community-CI: Broadcom CI <spdk-ci.pdl@broadcom.com> Reviewed-by: Shuhei Matsumoto <smatsumoto@nvidia.com> Reviewed-by: Konrad Sztyber <konrad.sztyber@intel.com> Community-CI: Community CI Samsung <spdk.community.ci.samsung@gmail.com> Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
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| b37db069 | 03-Dec-2024 |
XuQi <1530865185@qq.com> |
replace strtok with strtok_r
The strtok function is not reentrant. To address this issue in a multithreaded environment, the strtok_r function should be used, which is the reentrant version of strto
replace strtok with strtok_r
The strtok function is not reentrant. To address this issue in a multithreaded environment, the strtok_r function should be used, which is the reentrant version of strtok.
Signed-off-by: XuQi <1530865185@qq.com> Change-Id: I35c07c7cf4e20bacb7b1e7c7adaedfcd1a81f86e Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/25492 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Changpeng Liu <changpeliu@tencent.com> Reviewed-by: Jim Harris <jim.harris@nvidia.com> Community-CI: Community CI Samsung <spdk.community.ci.samsung@gmail.com> Community-CI: Mellanox Build Bot
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| a59d7e01 | 18-Jul-2024 |
Alexey Marchuk <alexeymar@nvidia.com> |
lib/mlx5: Add API to check if UMR registration supported
The 2 new APIs are used for negotiation between different modules to use accel sequence/UMR
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.
lib/mlx5: Add API to check if UMR registration supported
The 2 new APIs are used for negotiation between different modules to use accel sequence/UMR
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: Ifca6a3e3a7649e48392785d7a977e1b468dbf4be Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/24700 Reviewed-by: Shuhei Matsumoto <smatsumoto@nvidia.com> Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Konrad Sztyber <konrad.sztyber@intel.com> Community-CI: Broadcom CI <spdk-ci.pdl@broadcom.com> Community-CI: Community CI Samsung <spdk.community.ci.samsung@gmail.com> Community-CI: Mellanox Build Bot
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| f6925f5e | 18-Jul-2024 |
Alexey Marchuk <alexeymar@nvidia.com> |
accel/mlx5: Merge crypto+copy to reg UMR
Nvidia ConnectX offloads work with verbs semanthic where an offload is a property of a Memory Key. We can change Memeory Key properties in IO path by submitt
accel/mlx5: Merge crypto+copy to reg UMR
Nvidia ConnectX offloads work with verbs semanthic where an offload is a property of a Memory Key. We can change Memeory Key properties in IO path by submitting a special Work Request. Result is a User Memory Region (UMR). When NIC performs RDMA_READ/WRITE or send operation with this UMR, HW detects special properties of a memory key and applies these properties. For NVMEoF RDMA protocol that means that we can register UMR with e.g. encrypt/decrypt and send it in NVMF capsule to remote target. When target does RDMA_READ/WRITE, local NIC first applies crypto to the memory buffer and then executes RDMA operation. In case of encryption, data remains unencrypted in the host memory and encrypted during transmission to the wire. This patch is the first step to enable accel operations in nvme_rdma driver. We detect a sequence of encrypt+copy(rdma domain) or copy(rdma domain)+decrypt and treat such a sequence as UMR registration (without RDMA operation). Result of the sequence is UMR. To return UMR to the caller, memory domain in the copy task must support data transfer operation.
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: I1cafb4dbf6da4b16f416d4e82078982494858bc2 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/24699 Reviewed-by: Ben Walker <ben@nvidia.com> Community-CI: Mellanox Build Bot Reviewed-by: Shuhei Matsumoto <smatsumoto@nvidia.com> Community-CI: Broadcom CI <spdk-ci.pdl@broadcom.com> Community-CI: Community CI Samsung <spdk.community.ci.samsung@gmail.com> Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
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| 008a6371 | 05-Jul-2024 |
Alexey Marchuk <alexeymar@nvidia.com> |
accel/mlx5: Initial implementation of mlx5 platform driver
Now we just execute all tasks one by one. The driver supports only limited scope of operations and disabled by default
Signed-off-by: Alex
accel/mlx5: Initial implementation of mlx5 platform driver
Now we just execute all tasks one by one. The driver supports only limited scope of operations and disabled by default
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: I1478db685b1621a4610be1c80929d62d1106e908 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/24698 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Ben Walker <ben@nvidia.com> Community-CI: Mellanox Build Bot Reviewed-by: Shuhei Matsumoto <smatsumoto@nvidia.com> Community-CI: Broadcom CI <spdk-ci.pdl@broadcom.com> Community-CI: Community CI Samsung <spdk.community.ci.samsung@gmail.com>
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| 11789573 | 18-Jul-2024 |
Alexey Marchuk <alexeymar@nvidia.com> |
accel/mlx5: Factor out task submissions
Move qp assignment to a function, that reduces changes in next patch
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: Icb63962e8dfad6671cbe25a
accel/mlx5: Factor out task submissions
Move qp assignment to a function, that reduces changes in next patch
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: Icb63962e8dfad6671cbe25aee4b27a8beabd58c4 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/24697 Community-CI: Mellanox Build Bot Reviewed-by: Shuhei Matsumoto <smatsumoto@nvidia.com> Community-CI: Broadcom CI <spdk-ci.pdl@broadcom.com> Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Ben Walker <ben@nvidia.com> Community-CI: Community CI Samsung <spdk.community.ci.samsung@gmail.com>
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| 6438af6b | 11-Sep-2024 |
Alexey Marchuk <alexeymar@nvidia.com> |
accel/mlx5: Fix memleak in mlx5_scan_accel_module RPC
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: I572d0b54905b8f8c417f8f0acfaf80e62d76a448 Reviewed-on: https://review.spdk.io/ge
accel/mlx5: Fix memleak in mlx5_scan_accel_module RPC
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: I572d0b54905b8f8c417f8f0acfaf80e62d76a448 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/24876 Community-CI: Mellanox Build Bot Reviewed-by: Ben Walker <ben@nvidia.com> Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Konrad Sztyber <konrad.sztyber@intel.com> Community-CI: Broadcom CI <spdk-ci.pdl@broadcom.com>
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| fe7bb7bd | 10-May-2024 |
Alexey Marchuk <alexeymar@nvidia.com> |
accel/mlx5: Add statistics
Collect statistics per accel opcode, per mlx5 operation, polling and nomem statistics The statistics can be retrieved per channel, per device per channel and accumulated p
accel/mlx5: Add statistics
Collect statistics per accel opcode, per mlx5 operation, polling and nomem statistics The statistics can be retrieved per channel, per device per channel and accumulated per module
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: I082e1556295071d0243037fd810bb6ade752c352 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/23141 Reviewed-by: Shuhei Matsumoto <smatsumoto@nvidia.com> Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Community-CI: Broadcom CI <spdk-ci.pdl@broadcom.com> Community-CI: Mellanox Build Bot Reviewed-by: Konrad Sztyber <konrad.sztyber@intel.com>
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| 64627ae7 | 08-May-2024 |
Alexey Marchuk <alexeymar@nvidia.com> |
accel/mlx5: Support crc32c offload
Add tests to verify the crc32c with mlx5 module
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Signed-off-by: Sergey Gorenko <sergeygo@nvidia.com> Change-Id
accel/mlx5: Support crc32c offload
Add tests to verify the crc32c with mlx5 module
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Signed-off-by: Sergey Gorenko <sergeygo@nvidia.com> Change-Id: I65a517d69fe12abd01e7f5d2f5b1c7da80883f40 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/23140 Reviewed-by: Shuhei Matsumoto <smatsumoto@nvidia.com> Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Konrad Sztyber <konrad.sztyber@intel.com> Community-CI: Mellanox Build Bot Community-CI: Broadcom CI <spdk-ci.pdl@broadcom.com>
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| 6e947066 | 10-May-2024 |
Alexey Marchuk <alexeymar@nvidia.com> |
accel/mlx5: Checking the minimum module configuration values
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: If2f32b8044cd408bfbab24423e989dabd6c86d38 Reviewed-on: https://review.spd
accel/mlx5: Checking the minimum module configuration values
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: If2f32b8044cd408bfbab24423e989dabd6c86d38 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/23138 Reviewed-by: Jim Harris <jim.harris@samsung.com> Reviewed-by: Shuhei Matsumoto <smatsumoto@nvidia.com> Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Ben Walker <ben@nvidia.com> Community-CI: Mellanox Build Bot
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| 2f974243 | 08-May-2024 |
Alexey Marchuk <alexeymar@nvidia.com> |
accel/mlx5: Detect crc32c capabilities
Check if a device supports crc32 offload and initialize signature mkeys and PSVs pool. Preparation step to support crc32c accel opcode
Signed-off-by: Alexey M
accel/mlx5: Detect crc32c capabilities
Check if a device supports crc32 offload and initialize signature mkeys and PSVs pool. Preparation step to support crc32c accel opcode
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: Id7e83b36384f24bbeb097d1b686e852efb680342 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/23137 Reviewed-by: Ben Walker <ben@nvidia.com> Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Community-CI: Mellanox Build Bot Reviewed-by: Jim Harris <jim.harris@samsung.com>
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| d987d777 | 07-May-2024 |
Alexey Marchuk <alexeymar@nvidia.com> |
accel/mlx5: Support copy operation
Since number of iovs per 1 RDMA operation is limited by 16, we have to caculate the number of operations which must be completed. In the worst case we have to iter
accel/mlx5: Support copy operation
Since number of iovs per 1 RDMA operation is limited by 16, we have to caculate the number of operations which must be completed. In the worst case we have to iterate both src and dst iovs to find this number. Added a test with malloc bdev to check the new copy operation.
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: I8bc75813f94d8fdff2e0af5cf5b8c254d8042af9 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/23135 Reviewed-by: Jim Harris <jim.harris@samsung.com> Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Community-CI: Mellanox Build Bot Reviewed-by: Ben Walker <ben@nvidia.com> Reviewed-by: Shuhei Matsumoto <smatsumoto@nvidia.com>
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| 15e9c8ba | 07-May-2024 |
Alexey Marchuk <alexeymar@nvidia.com> |
accel/mlx5: Task processing functions
Add a struct with 4 fn pointers to init, process, continue and finish a task. That allows us to add new opcodes with less effort
Signed-off-by: Alexey Marchuk
accel/mlx5: Task processing functions
Add a struct with 4 fn pointers to init, process, continue and finish a task. That allows us to add new opcodes with less effort
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: I37e85e5d34a1c5989675c1b9df66055f8c641b30 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/23131 Reviewed-by: Jim Harris <jim.harris@samsung.com> Reviewed-by: Shuhei Matsumoto <smatsumoto@nvidia.com> Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Community-CI: Mellanox Build Bot Reviewed-by: Ben Walker <ben@nvidia.com>
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| e321b863 | 06-May-2024 |
Alexey Marchuk <alexeymar@nvidia.com> |
acce/mlx5: Rename internal structs
Remove `crypto` from struct names
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: Ie3d20c3ec2f0b941e3c4eefebd0dc637aaa8478a Reviewed-on: https://r
acce/mlx5: Rename internal structs
Remove `crypto` from struct names
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: Ie3d20c3ec2f0b941e3c4eefebd0dc637aaa8478a Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/23130 Reviewed-by: Shuhei Matsumoto <smatsumoto@nvidia.com> Community-CI: Mellanox Build Bot Reviewed-by: Ben Walker <ben@nvidia.com> Tested-by: SPDK CI Jenkins <sys_sgci@intel.com>
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| cfe8f56f | 03-May-2024 |
Alexey Marchuk <alexeymar@nvidia.com> |
accel/mlx5: Support highly fragmented payload
Each crypto operation can use up to 16 iov elements, it is enough in most cases. But in case of high memory fragmentation, we need to unwind pointers to
accel/mlx5: Support highly fragmented payload
Each crypto operation can use up to 16 iov elements, it is enough in most cases. But in case of high memory fragmentation, we need to unwind pointers to the previous data block and execute extra crypto oepration
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: I586646099c90f4c700941fb44320c11cd863254e Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/23128 Community-CI: Mellanox Build Bot Reviewed-by: Ben Walker <ben@nvidia.com> Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Shuhei Matsumoto <smatsumoto@nvidia.com>
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| 7f76f056 | 03-May-2024 |
Alexey Marchuk <alexeymar@nvidia.com> |
accel/mlx5: Add qp recovery
Detect WC with error, wait for qp to become empty and re-create it
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: I72a4967160fcb0e9344acaf75beb2578996ac
accel/mlx5: Add qp recovery
Detect WC with error, wait for qp to become empty and re-create it
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: I72a4967160fcb0e9344acaf75beb2578996acf52 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/23126 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Shuhei Matsumoto <smatsumoto@nvidia.com> Community-CI: Mellanox Build Bot Reviewed-by: Ben Walker <ben@nvidia.com>
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| 5a5361ce | 03-May-2024 |
Alexey Marchuk <alexeymar@nvidia.com> |
accel/mlx5: Correct qp slot check, mkey allocation
Number of mkeys allocated do not depend on the available qp slot. When a task is being executed, number of operations is limited by qp slot. Take i
accel/mlx5: Correct qp slot check, mkey allocation
Number of mkeys allocated do not depend on the available qp slot. When a task is being executed, number of operations is limited by qp slot. Take into account that crypto requires at least 2 qp slots
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: If33da6cbd591a94e6318bcfa582998d22cff4eb3 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/23125 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Ben Walker <ben@nvidia.com> Reviewed-by: Shuhei Matsumoto <smatsumoto@nvidia.com> Community-CI: Mellanox Build Bot
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| a1a81923 | 03-May-2024 |
Alexey Marchuk <alexeymar@nvidia.com> |
accel/mxl5: Use memcmp to compare iovs
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: If37062a02f302831b6c851cf092bf18f4e1a640f Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spd
accel/mxl5: Use memcmp to compare iovs
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: If37062a02f302831b6c851cf092bf18f4e1a640f Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/23124 Community-CI: Mellanox Build Bot Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Ben Walker <ben@nvidia.com> Reviewed-by: Shuhei Matsumoto <smatsumoto@nvidia.com>
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| 73d53a6c | 03-May-2024 |
Alexey Marchuk <alexeymar@nvidia.com> |
accel/mlx5: Further reduce size of task struct
Use bitfields for `inplace` and 'enc_order' members, use STAILQ instead of TAILQ Reorder structure to keep big member at the beginning
Signed-off-by:
accel/mlx5: Further reduce size of task struct
Use bitfields for `inplace` and 'enc_order' members, use STAILQ instead of TAILQ Reorder structure to keep big member at the beginning
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: I416a37c03cc0dd3d73fef9e811d91964ef352407 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/23123 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Shuhei Matsumoto <smatsumoto@nvidia.com> Community-CI: Mellanox Build Bot Reviewed-by: Ben Walker <ben@nvidia.com>
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| 8b432db5 | 03-May-2024 |
Alexey Marchuk <alexeymar@nvidia.com> |
accel/mlx5: Reduce size of task struct - narrow int type
uint16_t should be enough for most common use cases. Max size of a single op which can be handled is limited by num_blocks, so that is 512B*6
accel/mlx5: Reduce size of task struct - narrow int type
uint16_t should be enough for most common use cases. Max size of a single op which can be handled is limited by num_blocks, so that is 512B*65535~32MiB Add asserts to catch uint16 overflow Reduce size of counters in accel_mlx5_qp as well
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: I1d31f0d536bb15887d8d5b4365dcd79dd7f80ac6 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/23122 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Shuhei Matsumoto <smatsumoto@nvidia.com> Community-CI: Mellanox Build Bot Reviewed-by: Ben Walker <ben@nvidia.com>
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| 8f7b0419 | 02-May-2024 |
Alexey Marchuk <alexeymar@nvidia.com> |
accel/mlx5: Rework task completion
- Add a function to fail a task, remove `rc` field from the accel_mlx5_task structure. - Fix num_completed_reqs calculation - Remove condition to continue a task -
accel/mlx5: Rework task completion
- Add a function to fail a task, remove `rc` field from the accel_mlx5_task structure. - Fix num_completed_reqs calculation - Remove condition to continue a task - we always reap 1 completion per sumbission
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: Icfc9c0261d20d83d0f6120ede30730e5fde6b409 Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/23121 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Ben Walker <ben@nvidia.com> Community-CI: Mellanox Build Bot Reviewed-by: Shuhei Matsumoto <smatsumoto@nvidia.com>
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| 81a4f3e5 | 02-May-2024 |
Alexey Marchuk <alexeymar@nvidia.com> |
accel/mlx5: Factor out free qp slot calculation
Move slots calc logic to a new function, take into account cq capacity.
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: I359f5e6a0eeb
accel/mlx5: Factor out free qp slot calculation
Move slots calc logic to a new function, take into account cq capacity.
Signed-off-by: Alexey Marchuk <alexeymar@nvidia.com> Change-Id: I359f5e6a0eebc73bfc1b9de1091ced7991a6f8ee Reviewed-on: https://review.spdk.io/gerrit/c/spdk/spdk/+/23120 Tested-by: SPDK CI Jenkins <sys_sgci@intel.com> Reviewed-by: Ben Walker <ben@nvidia.com> Community-CI: Mellanox Build Bot Reviewed-by: Shuhei Matsumoto <smatsumoto@nvidia.com>
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