Ensure XHCI_SCTX_DCI() always contains a valid number, i.e. the DCI of
the highest active endpoint context.

Don't zap other fields when setting XHCI_SCTX_DCI().

Fixes (at least) Etron EJ168 USB 3.0

Ensure XHCI_SCTX_DCI() always contains a valid number, i.e. the DCI of
the highest active endpoint context.

Don't zap other fields when setting XHCI_SCTX_DCI().

Fixes (at least) Etron EJ168 USB 3.0 Host Controllers vs USB 2
devices.

Inspired by hselasky FreeBSD revision 243780.

Feedback from kn@, ok beck@ (previous iteration) patrick@

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On short transfers with multiple TRBs in a TD we get two events.
One on the TRB that went short, and one for the last TRB in a TD.
We already set actlen only once so that the last TRB in a TD does
no

On short transfers with multiple TRBs in a TD we get two events.
One on the TRB that went short, and one for the last TRB in a TD.
We already set actlen only once so that the last TRB in a TD does
not override it, but some controllers throw another short event
instead of a success event, so we have to add the same check there
as well.

ok gerhard@ mglocker@

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Fix off-by-one TRB issue in bulk transfers larger than 64k.
This makes udl(4) on xhci(4) work fine.

Help and ok patrick@

Fix actual length calculation of short transfers in xhci(4). So far
we have subtracted the remaining length from the total transfer
length, which essentially means that we assume that all TRBs have

Fix actual length calculation of short transfers in xhci(4). So far
we have subtracted the remaining length from the total transfer
length, which essentially means that we assume that all TRBs have
successfully been transferred apart from the remainder. Actually
we might get a short completion in the middle of a chain of TRBs,
which means that all TRBs until this TRB have completed successfully
apart from a remainder. Thus we have to count the length of all
TRBs until and including the one that we went short on, and remove
the remainder. All following TRBs in the same transfer must be
ignored.

Found by and fixed with gerhard@
ok mglocker@

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Use MSEC_TO_NSEC() to define XHCI_CMD_TIMEOUT & use it w/ tsleep_nsec(9).

ok visa@, kn@

Do not consider the pipe as halted if the device is gone.

Analysed by and ok claudio@

Fix NULL check with wrong pointer in xhci_event_xfer_isoc(); CID 1480287
ok ratchov@

Decrease verbosity when XHCI_DEBUG is defined.

ok mpi

Handle missed service errors, specific to isochronous transfers.

After each MSE, ensuire usbd_complete_transfer() is called for each
missed transfer, for which there's no transfer completion event.

Handle missed service errors, specific to isochronous transfers.

After each MSE, ensuire usbd_complete_transfer() is called for each
missed transfer, for which there's no transfer completion event. Fixes
crashes and deadlocks in upper layers caused by the missing
completion.

ok deraadt, patrick; help from mpi, patrick, gmlocker

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Since an isoc endpoint never halts, move to remaining error handling
code in xhci_event_xfer() to the generic handler function.

suggested and ok mpi@

Move the handler code in the xhci_event_xfer() switch case in two separate
functions for isoc and !isoc xfers.

Suggested by mpi@.

ok patrick@, stsp@

Remove obsolete semicolon at end of case switch.

Merge the duplicate code to handle isoc SHORT and SUCCESS xfer events
to one single function.

ok mpi@

Improve and enable isochronous transfers in xhci(4). Each isochronous
frame has to be enqueued as Transfer Descriptor. This means each frame
starts with an isoch TRB and may also contain further no

Improve and enable isochronous transfers in xhci(4). Each isochronous
frame has to be enqueued as Transfer Descriptor. This means each frame
starts with an isoch TRB and may also contain further normal TRBs. The
TDs each throw at least one interrupt for a successful completion or
possibly more in case of a short xfer. We have to account the amount
of data transfered for each frame using the completion of the matching
TD and its TRBs.

Thanks to stsp@ for initiating this, and many more thanks to mglocker@
for reworking and cleaning up my initial diff. Further improvements
can happen in-tree now.

Tested by mglocker@, phessler@ and stsp@
ok mglocker@, stsp@

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The max burst size that is encoded in wMaxPacketSize is zero based,
as in: Since there's always one transfer, 0 means 1. Thus we have
to add 1 (not OR) to get to the desired number.

ok mglocker@ m

The max burst size that is encoded in wMaxPacketSize is zero based,
as in: Since there's always one transfer, 0 means 1. Thus we have
to add 1 (not OR) to get to the desired number.

ok mglocker@ mpi@ stsp@

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Fix typo in debug print: wih -> with

ok mpi@

Add missing bus powered bit, from aalm@

Since ring->index points to the next free slot, once we reach index zero
we know that the last non-link TRB has been written and we can look at
the flags to set the chain bit in the link TRB. Since

Since ring->index points to the next free slot, once we reach index zero
we know that the last non-link TRB has been written and we can look at
the flags to set the chain bit in the link TRB. Since we will now toggle
the cycle bit on the first TRB of a ring, set it on the ring reset.

Tested by jcs@, jsg@ and visa@
"commit it" jcs@

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Make xhci_ring_produce() check the previous TRB to find out if it
needs the Chain Bit set or not instead of using the last parameter,
which is used to mark the last TRB in a USB transfer, not in a TD

Make xhci_ring_produce() check the previous TRB to find out if it
needs the Chain Bit set or not instead of using the last parameter,
which is used to mark the last TRB in a USB transfer, not in a TD.
To make that work we need to setup the recently acquired TRB before
calling xhci_xfer_get_trb() the next time. Thus setting up the
initial TRB has to happen right away. To kick the transfer off we
simply flip the toggle bit on the first TRB right at the end.

Fixes regression for jcs@, dhill@ and stsp@
Initially discussed with mpi@
ok stsp@

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Transfers that span multiple TRBs which wrap around the ring and
thus have the Link TRB inbetween must have the Chain Bit set in the
Link TRB. Otherwise xHCI controllers might think that the transfe

Transfers that span multiple TRBs which wrap around the ring and
thus have the Link TRB inbetween must have the Chain Bit set in the
Link TRB. Otherwise xHCI controllers might think that the transfer
ends at that point.

Fixes an issue that was most prominently seen as Invalid CSW error
when using umass0 on octeon and i.MX8M.

Tested by visa@
ok mpi@

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Print xhci version in hex, from sc.dying at gmail.

If we cannot stop the endpoint when aborting a transfer assume that
the device is gone and give back the descriptor to the stack.

Without this usbd_abort_pipe() could end up in an infinite loop.

Is

If we cannot stop the endpoint when aborting a transfer assume that
the device is gone and give back the descriptor to the stack.

Without this usbd_abort_pipe() could end up in an infinite loop.

Issue reported by Tom Murphy.

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Serialize synchronous commands with a rwlock.

Prevent triggering an assert if two drivers try to submit a command
at the same time.

Issue reported by Tom Murphy.

typos, from Michael W. Bombardieri.

Add bus DMA barriers to ensure the hardware does not see a TRB cycle bit
flip before the rest of the TRB is updated.

OK dlg@, pirofti@, mpi@