1 /* $OpenBSD: xhci.c,v 1.105 2019/06/13 21:03:48 mpi Exp $ */ 2 3 /* 4 * Copyright (c) 2014-2015 Martin Pieuchot 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include <sys/param.h> 20 #include <sys/systm.h> 21 #include <sys/kernel.h> 22 #include <sys/malloc.h> 23 #include <sys/device.h> 24 #include <sys/queue.h> 25 #include <sys/timeout.h> 26 #include <sys/pool.h> 27 #include <sys/endian.h> 28 #include <sys/rwlock.h> 29 30 #include <machine/bus.h> 31 32 #include <dev/usb/usb.h> 33 #include <dev/usb/usbdi.h> 34 #include <dev/usb/usbdivar.h> 35 #include <dev/usb/usb_mem.h> 36 37 #include <dev/usb/xhcireg.h> 38 #include <dev/usb/xhcivar.h> 39 40 struct cfdriver xhci_cd = { 41 NULL, "xhci", DV_DULL 42 }; 43 44 #ifdef XHCI_DEBUG 45 #define DPRINTF(x) do { if (xhcidebug) printf x; } while(0) 46 #define DPRINTFN(n,x) do { if (xhcidebug>(n)) printf x; } while (0) 47 int xhcidebug = 3; 48 #else 49 #define DPRINTF(x) 50 #define DPRINTFN(n,x) 51 #endif 52 53 #define DEVNAME(sc) ((sc)->sc_bus.bdev.dv_xname) 54 55 #define TRBOFF(r, trb) ((char *)(trb) - (char *)((r)->trbs)) 56 #define DEQPTR(r) ((r).dma.paddr + (sizeof(struct xhci_trb) * (r).index)) 57 58 struct pool *xhcixfer; 59 60 struct xhci_pipe { 61 struct usbd_pipe pipe; 62 63 uint8_t dci; 64 uint8_t slot; /* Device slot ID */ 65 struct xhci_ring ring; 66 67 /* 68 * XXX used to pass the xfer pointer back to the 69 * interrupt routine, better way? 70 */ 71 struct usbd_xfer *pending_xfers[XHCI_MAX_XFER]; 72 struct usbd_xfer *aborted_xfer; 73 int halted; 74 size_t free_trbs; 75 int skip; 76 }; 77 78 int xhci_reset(struct xhci_softc *); 79 int xhci_intr1(struct xhci_softc *); 80 void xhci_event_dequeue(struct xhci_softc *); 81 void xhci_event_xfer(struct xhci_softc *, uint64_t, uint32_t, uint32_t); 82 int xhci_event_xfer_generic(struct xhci_softc *, struct usbd_xfer *, 83 struct xhci_pipe *, uint32_t, int, uint8_t, uint8_t, uint8_t); 84 int xhci_event_xfer_isoc(struct usbd_xfer *, struct xhci_pipe *, 85 uint32_t, int); 86 void xhci_event_command(struct xhci_softc *, uint64_t); 87 void xhci_event_port_change(struct xhci_softc *, uint64_t, uint32_t); 88 int xhci_pipe_init(struct xhci_softc *, struct usbd_pipe *); 89 int xhci_context_setup(struct xhci_softc *, struct usbd_pipe *); 90 int xhci_scratchpad_alloc(struct xhci_softc *, int); 91 void xhci_scratchpad_free(struct xhci_softc *); 92 int xhci_softdev_alloc(struct xhci_softc *, uint8_t); 93 void xhci_softdev_free(struct xhci_softc *, uint8_t); 94 int xhci_ring_alloc(struct xhci_softc *, struct xhci_ring *, size_t, 95 size_t); 96 void xhci_ring_free(struct xhci_softc *, struct xhci_ring *); 97 void xhci_ring_reset(struct xhci_softc *, struct xhci_ring *); 98 struct xhci_trb *xhci_ring_consume(struct xhci_softc *, struct xhci_ring *); 99 struct xhci_trb *xhci_ring_produce(struct xhci_softc *, struct xhci_ring *); 100 101 struct xhci_trb *xhci_xfer_get_trb(struct xhci_softc *, struct usbd_xfer*, 102 uint8_t *, int); 103 void xhci_xfer_done(struct usbd_xfer *xfer); 104 /* xHCI command helpers. */ 105 int xhci_command_submit(struct xhci_softc *, struct xhci_trb *, int); 106 int xhci_command_abort(struct xhci_softc *); 107 108 void xhci_cmd_reset_ep_async(struct xhci_softc *, uint8_t, uint8_t); 109 void xhci_cmd_set_tr_deq_async(struct xhci_softc *, uint8_t, uint8_t, uint64_t); 110 int xhci_cmd_configure_ep(struct xhci_softc *, uint8_t, uint64_t); 111 int xhci_cmd_stop_ep(struct xhci_softc *, uint8_t, uint8_t); 112 int xhci_cmd_slot_control(struct xhci_softc *, uint8_t *, int); 113 int xhci_cmd_set_address(struct xhci_softc *, uint8_t, uint64_t, uint32_t); 114 int xhci_cmd_evaluate_ctx(struct xhci_softc *, uint8_t, uint64_t); 115 #ifdef XHCI_DEBUG 116 int xhci_cmd_noop(struct xhci_softc *); 117 #endif 118 119 /* XXX should be part of the Bus interface. */ 120 void xhci_abort_xfer(struct usbd_xfer *, usbd_status); 121 void xhci_pipe_close(struct usbd_pipe *); 122 void xhci_noop(struct usbd_xfer *); 123 124 void xhci_timeout(void *); 125 void xhci_timeout_task(void *); 126 127 /* USBD Bus Interface. */ 128 usbd_status xhci_pipe_open(struct usbd_pipe *); 129 int xhci_setaddr(struct usbd_device *, int); 130 void xhci_softintr(void *); 131 void xhci_poll(struct usbd_bus *); 132 struct usbd_xfer *xhci_allocx(struct usbd_bus *); 133 void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 135 usbd_status xhci_root_ctrl_transfer(struct usbd_xfer *); 136 usbd_status xhci_root_ctrl_start(struct usbd_xfer *); 137 138 usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 139 usbd_status xhci_root_intr_start(struct usbd_xfer *); 140 void xhci_root_intr_abort(struct usbd_xfer *); 141 void xhci_root_intr_done(struct usbd_xfer *); 142 143 usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 144 usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 145 void xhci_device_ctrl_abort(struct usbd_xfer *); 146 147 usbd_status xhci_device_generic_transfer(struct usbd_xfer *); 148 usbd_status xhci_device_generic_start(struct usbd_xfer *); 149 void xhci_device_generic_abort(struct usbd_xfer *); 150 void xhci_device_generic_done(struct usbd_xfer *); 151 152 usbd_status xhci_device_isoc_transfer(struct usbd_xfer *); 153 usbd_status xhci_device_isoc_start(struct usbd_xfer *); 154 155 #define XHCI_INTR_ENDPT 1 156 157 struct usbd_bus_methods xhci_bus_methods = { 158 .open_pipe = xhci_pipe_open, 159 .dev_setaddr = xhci_setaddr, 160 .soft_intr = xhci_softintr, 161 .do_poll = xhci_poll, 162 .allocx = xhci_allocx, 163 .freex = xhci_freex, 164 }; 165 166 struct usbd_pipe_methods xhci_root_ctrl_methods = { 167 .transfer = xhci_root_ctrl_transfer, 168 .start = xhci_root_ctrl_start, 169 .abort = xhci_noop, 170 .close = xhci_pipe_close, 171 .done = xhci_noop, 172 }; 173 174 struct usbd_pipe_methods xhci_root_intr_methods = { 175 .transfer = xhci_root_intr_transfer, 176 .start = xhci_root_intr_start, 177 .abort = xhci_root_intr_abort, 178 .close = xhci_pipe_close, 179 .done = xhci_root_intr_done, 180 }; 181 182 struct usbd_pipe_methods xhci_device_ctrl_methods = { 183 .transfer = xhci_device_ctrl_transfer, 184 .start = xhci_device_ctrl_start, 185 .abort = xhci_device_ctrl_abort, 186 .close = xhci_pipe_close, 187 .done = xhci_noop, 188 }; 189 190 struct usbd_pipe_methods xhci_device_intr_methods = { 191 .transfer = xhci_device_generic_transfer, 192 .start = xhci_device_generic_start, 193 .abort = xhci_device_generic_abort, 194 .close = xhci_pipe_close, 195 .done = xhci_device_generic_done, 196 }; 197 198 struct usbd_pipe_methods xhci_device_bulk_methods = { 199 .transfer = xhci_device_generic_transfer, 200 .start = xhci_device_generic_start, 201 .abort = xhci_device_generic_abort, 202 .close = xhci_pipe_close, 203 .done = xhci_device_generic_done, 204 }; 205 206 struct usbd_pipe_methods xhci_device_isoc_methods = { 207 .transfer = xhci_device_isoc_transfer, 208 .start = xhci_device_isoc_start, 209 .abort = xhci_device_generic_abort, 210 .close = xhci_pipe_close, 211 .done = xhci_noop, 212 }; 213 214 #ifdef XHCI_DEBUG 215 static void 216 xhci_dump_trb(struct xhci_trb *trb) 217 { 218 printf("trb=%p (0x%016llx 0x%08x 0x%b)\n", trb, 219 (long long)letoh64(trb->trb_paddr), letoh32(trb->trb_status), 220 (int)letoh32(trb->trb_flags), XHCI_TRB_FLAGS_BITMASK); 221 } 222 #endif 223 224 int usbd_dma_contig_alloc(struct usbd_bus *, struct usbd_dma_info *, 225 void **, bus_size_t, bus_size_t, bus_size_t); 226 void usbd_dma_contig_free(struct usbd_bus *, struct usbd_dma_info *); 227 228 int 229 usbd_dma_contig_alloc(struct usbd_bus *bus, struct usbd_dma_info *dma, 230 void **kvap, bus_size_t size, bus_size_t alignment, bus_size_t boundary) 231 { 232 int error; 233 234 dma->tag = bus->dmatag; 235 dma->size = size; 236 237 error = bus_dmamap_create(dma->tag, size, 1, size, boundary, 238 BUS_DMA_NOWAIT, &dma->map); 239 if (error != 0) 240 return (error); 241 242 error = bus_dmamem_alloc(dma->tag, size, alignment, boundary, &dma->seg, 243 1, &dma->nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 244 if (error != 0) 245 goto destroy; 246 247 error = bus_dmamem_map(dma->tag, &dma->seg, 1, size, &dma->vaddr, 248 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 249 if (error != 0) 250 goto free; 251 252 error = bus_dmamap_load_raw(dma->tag, dma->map, &dma->seg, 1, size, 253 BUS_DMA_NOWAIT); 254 if (error != 0) 255 goto unmap; 256 257 bus_dmamap_sync(dma->tag, dma->map, 0, size, BUS_DMASYNC_PREREAD | 258 BUS_DMASYNC_PREWRITE); 259 260 dma->paddr = dma->map->dm_segs[0].ds_addr; 261 if (kvap != NULL) 262 *kvap = dma->vaddr; 263 264 return (0); 265 266 unmap: 267 bus_dmamem_unmap(dma->tag, dma->vaddr, size); 268 free: 269 bus_dmamem_free(dma->tag, &dma->seg, 1); 270 destroy: 271 bus_dmamap_destroy(dma->tag, dma->map); 272 return (error); 273 } 274 275 void 276 usbd_dma_contig_free(struct usbd_bus *bus, struct usbd_dma_info *dma) 277 { 278 if (dma->map != NULL) { 279 bus_dmamap_sync(bus->dmatag, dma->map, 0, dma->size, 280 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 281 bus_dmamap_unload(bus->dmatag, dma->map); 282 bus_dmamem_unmap(bus->dmatag, dma->vaddr, dma->size); 283 bus_dmamem_free(bus->dmatag, &dma->seg, 1); 284 bus_dmamap_destroy(bus->dmatag, dma->map); 285 dma->map = NULL; 286 } 287 } 288 289 int 290 xhci_init(struct xhci_softc *sc) 291 { 292 uint32_t hcr; 293 int npage, error; 294 295 sc->sc_bus.usbrev = USBREV_3_0; 296 sc->sc_bus.methods = &xhci_bus_methods; 297 sc->sc_bus.pipe_size = sizeof(struct xhci_pipe); 298 299 sc->sc_oper_off = XREAD1(sc, XHCI_CAPLENGTH); 300 sc->sc_door_off = XREAD4(sc, XHCI_DBOFF); 301 sc->sc_runt_off = XREAD4(sc, XHCI_RTSOFF); 302 303 sc->sc_version = XREAD2(sc, XHCI_HCIVERSION); 304 printf(", xHCI %x.%x\n", sc->sc_version >> 8, sc->sc_version & 0xff); 305 306 #ifdef XHCI_DEBUG 307 printf("%s: CAPLENGTH=%#lx\n", DEVNAME(sc), sc->sc_oper_off); 308 printf("%s: DOORBELL=%#lx\n", DEVNAME(sc), sc->sc_door_off); 309 printf("%s: RUNTIME=%#lx\n", DEVNAME(sc), sc->sc_runt_off); 310 #endif 311 312 error = xhci_reset(sc); 313 if (error) 314 return (error); 315 316 if (xhcixfer == NULL) { 317 xhcixfer = malloc(sizeof(struct pool), M_DEVBUF, M_NOWAIT); 318 if (xhcixfer == NULL) { 319 printf("%s: unable to allocate pool descriptor\n", 320 DEVNAME(sc)); 321 return (ENOMEM); 322 } 323 pool_init(xhcixfer, sizeof(struct xhci_xfer), 0, IPL_SOFTUSB, 324 0, "xhcixfer", NULL); 325 } 326 327 hcr = XREAD4(sc, XHCI_HCCPARAMS); 328 sc->sc_ctxsize = XHCI_HCC_CSZ(hcr) ? 64 : 32; 329 DPRINTF(("%s: %d bytes context\n", DEVNAME(sc), sc->sc_ctxsize)); 330 331 #ifdef XHCI_DEBUG 332 hcr = XOREAD4(sc, XHCI_PAGESIZE); 333 printf("%s: supported page size 0x%08x\n", DEVNAME(sc), hcr); 334 #endif 335 /* Use 4K for the moment since it's easier. */ 336 sc->sc_pagesize = 4096; 337 338 /* Get port and device slot numbers. */ 339 hcr = XREAD4(sc, XHCI_HCSPARAMS1); 340 sc->sc_noport = XHCI_HCS1_N_PORTS(hcr); 341 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(hcr); 342 DPRINTF(("%s: %d ports and %d slots\n", DEVNAME(sc), sc->sc_noport, 343 sc->sc_noslot)); 344 345 /* Setup Device Context Base Address Array. */ 346 error = usbd_dma_contig_alloc(&sc->sc_bus, &sc->sc_dcbaa.dma, 347 (void **)&sc->sc_dcbaa.segs, (sc->sc_noslot + 1) * sizeof(uint64_t), 348 XHCI_DCBAA_ALIGN, sc->sc_pagesize); 349 if (error) 350 return (ENOMEM); 351 352 /* Setup command ring. */ 353 rw_init(&sc->sc_cmd_lock, "xhcicmd"); 354 error = xhci_ring_alloc(sc, &sc->sc_cmd_ring, XHCI_MAX_CMDS, 355 XHCI_CMDS_RING_ALIGN); 356 if (error) { 357 printf("%s: could not allocate command ring.\n", DEVNAME(sc)); 358 usbd_dma_contig_free(&sc->sc_bus, &sc->sc_dcbaa.dma); 359 return (error); 360 } 361 362 /* Setup one event ring and its segment table (ERST). */ 363 error = xhci_ring_alloc(sc, &sc->sc_evt_ring, XHCI_MAX_EVTS, 364 XHCI_EVTS_RING_ALIGN); 365 if (error) { 366 printf("%s: could not allocate event ring.\n", DEVNAME(sc)); 367 xhci_ring_free(sc, &sc->sc_cmd_ring); 368 usbd_dma_contig_free(&sc->sc_bus, &sc->sc_dcbaa.dma); 369 return (error); 370 } 371 372 /* Allocate the required entry for the segment table. */ 373 error = usbd_dma_contig_alloc(&sc->sc_bus, &sc->sc_erst.dma, 374 (void **)&sc->sc_erst.segs, sizeof(struct xhci_erseg), 375 XHCI_ERST_ALIGN, XHCI_ERST_BOUNDARY); 376 if (error) { 377 printf("%s: could not allocate segment table.\n", DEVNAME(sc)); 378 xhci_ring_free(sc, &sc->sc_evt_ring); 379 xhci_ring_free(sc, &sc->sc_cmd_ring); 380 usbd_dma_contig_free(&sc->sc_bus, &sc->sc_dcbaa.dma); 381 return (ENOMEM); 382 } 383 384 /* Set our ring address and size in its corresponding segment. */ 385 sc->sc_erst.segs[0].er_addr = htole64(sc->sc_evt_ring.dma.paddr); 386 sc->sc_erst.segs[0].er_size = htole32(XHCI_MAX_EVTS); 387 sc->sc_erst.segs[0].er_rsvd = 0; 388 bus_dmamap_sync(sc->sc_erst.dma.tag, sc->sc_erst.dma.map, 0, 389 sc->sc_erst.dma.size, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 390 391 /* Get the number of scratch pages and configure them if necessary. */ 392 hcr = XREAD4(sc, XHCI_HCSPARAMS2); 393 npage = XHCI_HCS2_SPB_MAX(hcr); 394 DPRINTF(("%s: %u scratch pages, ETE=%u, IST=0x%x\n", DEVNAME(sc), npage, 395 XHCI_HCS2_ETE(hcr), XHCI_HCS2_IST(hcr))); 396 397 if (npage > 0 && xhci_scratchpad_alloc(sc, npage)) { 398 printf("%s: could not allocate scratchpad.\n", DEVNAME(sc)); 399 usbd_dma_contig_free(&sc->sc_bus, &sc->sc_erst.dma); 400 xhci_ring_free(sc, &sc->sc_evt_ring); 401 xhci_ring_free(sc, &sc->sc_cmd_ring); 402 usbd_dma_contig_free(&sc->sc_bus, &sc->sc_dcbaa.dma); 403 return (ENOMEM); 404 } 405 406 407 return (0); 408 } 409 410 void 411 xhci_config(struct xhci_softc *sc) 412 { 413 uint64_t paddr; 414 uint32_t hcr; 415 416 /* Make sure to program a number of device slots we can handle. */ 417 if (sc->sc_noslot > USB_MAX_DEVICES) 418 sc->sc_noslot = USB_MAX_DEVICES; 419 hcr = XOREAD4(sc, XHCI_CONFIG) & ~XHCI_CONFIG_SLOTS_MASK; 420 XOWRITE4(sc, XHCI_CONFIG, hcr | sc->sc_noslot); 421 422 /* Set the device context base array address. */ 423 paddr = (uint64_t)sc->sc_dcbaa.dma.paddr; 424 XOWRITE4(sc, XHCI_DCBAAP_LO, (uint32_t)paddr); 425 XOWRITE4(sc, XHCI_DCBAAP_HI, (uint32_t)(paddr >> 32)); 426 427 DPRINTF(("%s: DCBAAP=%#x%#x\n", DEVNAME(sc), 428 XOREAD4(sc, XHCI_DCBAAP_HI), XOREAD4(sc, XHCI_DCBAAP_LO))); 429 430 /* Set the command ring address. */ 431 paddr = (uint64_t)sc->sc_cmd_ring.dma.paddr; 432 XOWRITE4(sc, XHCI_CRCR_LO, ((uint32_t)paddr) | XHCI_CRCR_LO_RCS); 433 XOWRITE4(sc, XHCI_CRCR_HI, (uint32_t)(paddr >> 32)); 434 435 DPRINTF(("%s: CRCR=%#x%#x (%016llx)\n", DEVNAME(sc), 436 XOREAD4(sc, XHCI_CRCR_HI), XOREAD4(sc, XHCI_CRCR_LO), paddr)); 437 438 /* Set the ERST count number to 1, since we use only one event ring. */ 439 XRWRITE4(sc, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(1)); 440 441 /* Set the segment table address. */ 442 paddr = (uint64_t)sc->sc_erst.dma.paddr; 443 XRWRITE4(sc, XHCI_ERSTBA_LO(0), (uint32_t)paddr); 444 XRWRITE4(sc, XHCI_ERSTBA_HI(0), (uint32_t)(paddr >> 32)); 445 446 DPRINTF(("%s: ERSTBA=%#x%#x\n", DEVNAME(sc), 447 XRREAD4(sc, XHCI_ERSTBA_HI(0)), XRREAD4(sc, XHCI_ERSTBA_LO(0)))); 448 449 /* Set the ring dequeue address. */ 450 paddr = (uint64_t)sc->sc_evt_ring.dma.paddr; 451 XRWRITE4(sc, XHCI_ERDP_LO(0), (uint32_t)paddr); 452 XRWRITE4(sc, XHCI_ERDP_HI(0), (uint32_t)(paddr >> 32)); 453 454 DPRINTF(("%s: ERDP=%#x%#x\n", DEVNAME(sc), 455 XRREAD4(sc, XHCI_ERDP_HI(0)), XRREAD4(sc, XHCI_ERDP_LO(0)))); 456 457 /* Enable interrupts. */ 458 hcr = XRREAD4(sc, XHCI_IMAN(0)); 459 XRWRITE4(sc, XHCI_IMAN(0), hcr | XHCI_IMAN_INTR_ENA); 460 461 /* Set default interrupt moderation. */ 462 XRWRITE4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT); 463 464 /* Allow event interrupt and start the controller. */ 465 XOWRITE4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); 466 467 DPRINTF(("%s: USBCMD=%#x\n", DEVNAME(sc), XOREAD4(sc, XHCI_USBCMD))); 468 DPRINTF(("%s: IMAN=%#x\n", DEVNAME(sc), XRREAD4(sc, XHCI_IMAN(0)))); 469 } 470 471 int 472 xhci_detach(struct device *self, int flags) 473 { 474 struct xhci_softc *sc = (struct xhci_softc *)self; 475 int rv; 476 477 rv = config_detach_children(self, flags); 478 if (rv != 0) { 479 printf("%s: error while detaching %d\n", DEVNAME(sc), rv); 480 return (rv); 481 } 482 483 /* Since the hardware might already be gone, ignore the errors. */ 484 xhci_command_abort(sc); 485 486 xhci_reset(sc); 487 488 /* Disable interrupts. */ 489 XRWRITE4(sc, XHCI_IMOD(0), 0); 490 XRWRITE4(sc, XHCI_IMAN(0), 0); 491 492 /* Clear the event ring address. */ 493 XRWRITE4(sc, XHCI_ERDP_LO(0), 0); 494 XRWRITE4(sc, XHCI_ERDP_HI(0), 0); 495 496 XRWRITE4(sc, XHCI_ERSTBA_LO(0), 0); 497 XRWRITE4(sc, XHCI_ERSTBA_HI(0), 0); 498 499 XRWRITE4(sc, XHCI_ERSTSZ(0), 0); 500 501 /* Clear the command ring address. */ 502 XOWRITE4(sc, XHCI_CRCR_LO, 0); 503 XOWRITE4(sc, XHCI_CRCR_HI, 0); 504 505 XOWRITE4(sc, XHCI_DCBAAP_LO, 0); 506 XOWRITE4(sc, XHCI_DCBAAP_HI, 0); 507 508 if (sc->sc_spad.npage > 0) 509 xhci_scratchpad_free(sc); 510 511 usbd_dma_contig_free(&sc->sc_bus, &sc->sc_erst.dma); 512 xhci_ring_free(sc, &sc->sc_evt_ring); 513 xhci_ring_free(sc, &sc->sc_cmd_ring); 514 usbd_dma_contig_free(&sc->sc_bus, &sc->sc_dcbaa.dma); 515 516 return (0); 517 } 518 519 int 520 xhci_activate(struct device *self, int act) 521 { 522 struct xhci_softc *sc = (struct xhci_softc *)self; 523 int rv = 0; 524 525 switch (act) { 526 case DVACT_RESUME: 527 sc->sc_bus.use_polling++; 528 529 xhci_reset(sc); 530 xhci_ring_reset(sc, &sc->sc_cmd_ring); 531 xhci_ring_reset(sc, &sc->sc_evt_ring); 532 533 /* Renesas controllers, at least, need more time to resume. */ 534 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 535 536 xhci_config(sc); 537 538 sc->sc_bus.use_polling--; 539 rv = config_activate_children(self, act); 540 break; 541 case DVACT_POWERDOWN: 542 rv = config_activate_children(self, act); 543 xhci_reset(sc); 544 break; 545 default: 546 rv = config_activate_children(self, act); 547 break; 548 } 549 550 return (rv); 551 } 552 553 int 554 xhci_reset(struct xhci_softc *sc) 555 { 556 uint32_t hcr; 557 int i; 558 559 XOWRITE4(sc, XHCI_USBCMD, 0); /* Halt controller */ 560 for (i = 0; i < 100; i++) { 561 usb_delay_ms(&sc->sc_bus, 1); 562 hcr = XOREAD4(sc, XHCI_USBSTS) & XHCI_STS_HCH; 563 if (hcr) 564 break; 565 } 566 567 if (!hcr) 568 printf("%s: halt timeout\n", DEVNAME(sc)); 569 570 XOWRITE4(sc, XHCI_USBCMD, XHCI_CMD_HCRST); 571 for (i = 0; i < 100; i++) { 572 usb_delay_ms(&sc->sc_bus, 1); 573 hcr = (XOREAD4(sc, XHCI_USBCMD) & XHCI_CMD_HCRST) | 574 (XOREAD4(sc, XHCI_USBSTS) & XHCI_STS_CNR); 575 if (!hcr) 576 break; 577 } 578 579 if (hcr) { 580 printf("%s: reset timeout\n", DEVNAME(sc)); 581 return (EIO); 582 } 583 584 return (0); 585 } 586 587 588 int 589 xhci_intr(void *v) 590 { 591 struct xhci_softc *sc = v; 592 593 if (sc == NULL || sc->sc_bus.dying) 594 return (0); 595 596 /* If we get an interrupt while polling, then just ignore it. */ 597 if (sc->sc_bus.use_polling) { 598 DPRINTFN(16, ("xhci_intr: ignored interrupt while polling\n")); 599 return (0); 600 } 601 602 return (xhci_intr1(sc)); 603 } 604 605 int 606 xhci_intr1(struct xhci_softc *sc) 607 { 608 uint32_t intrs; 609 610 intrs = XOREAD4(sc, XHCI_USBSTS); 611 if (intrs == 0xffffffff) { 612 sc->sc_bus.dying = 1; 613 return (0); 614 } 615 616 if ((intrs & XHCI_STS_EINT) == 0) 617 return (0); 618 619 sc->sc_bus.no_intrs++; 620 621 if (intrs & XHCI_STS_HSE) { 622 printf("%s: host system error\n", DEVNAME(sc)); 623 sc->sc_bus.dying = 1; 624 return (1); 625 } 626 627 XOWRITE4(sc, XHCI_USBSTS, intrs); /* Acknowledge */ 628 usb_schedsoftintr(&sc->sc_bus); 629 630 /* Acknowledge PCI interrupt */ 631 intrs = XRREAD4(sc, XHCI_IMAN(0)); 632 XRWRITE4(sc, XHCI_IMAN(0), intrs | XHCI_IMAN_INTR_PEND); 633 634 return (1); 635 } 636 637 void 638 xhci_poll(struct usbd_bus *bus) 639 { 640 struct xhci_softc *sc = (struct xhci_softc *)bus; 641 642 if (XOREAD4(sc, XHCI_USBSTS)) 643 xhci_intr1(sc); 644 } 645 646 void 647 xhci_softintr(void *v) 648 { 649 struct xhci_softc *sc = v; 650 651 if (sc->sc_bus.dying) 652 return; 653 654 sc->sc_bus.intr_context++; 655 xhci_event_dequeue(sc); 656 sc->sc_bus.intr_context--; 657 } 658 659 void 660 xhci_event_dequeue(struct xhci_softc *sc) 661 { 662 struct xhci_trb *trb; 663 uint64_t paddr; 664 uint32_t status, flags; 665 666 while ((trb = xhci_ring_consume(sc, &sc->sc_evt_ring)) != NULL) { 667 paddr = letoh64(trb->trb_paddr); 668 status = letoh32(trb->trb_status); 669 flags = letoh32(trb->trb_flags); 670 671 switch (flags & XHCI_TRB_TYPE_MASK) { 672 case XHCI_EVT_XFER: 673 xhci_event_xfer(sc, paddr, status, flags); 674 break; 675 case XHCI_EVT_CMD_COMPLETE: 676 memcpy(&sc->sc_result_trb, trb, sizeof(*trb)); 677 xhci_event_command(sc, paddr); 678 break; 679 case XHCI_EVT_PORT_CHANGE: 680 xhci_event_port_change(sc, paddr, status); 681 break; 682 case XHCI_EVT_HOST_CTRL: 683 /* TODO */ 684 break; 685 default: 686 #ifdef XHCI_DEBUG 687 printf("event (%d): ", XHCI_TRB_TYPE(flags)); 688 xhci_dump_trb(trb); 689 #endif 690 break; 691 } 692 693 } 694 695 paddr = (uint64_t)DEQPTR(sc->sc_evt_ring); 696 XRWRITE4(sc, XHCI_ERDP_LO(0), ((uint32_t)paddr) | XHCI_ERDP_LO_BUSY); 697 XRWRITE4(sc, XHCI_ERDP_HI(0), (uint32_t)(paddr >> 32)); 698 } 699 700 void 701 xhci_skip_all(struct xhci_pipe *xp) 702 { 703 struct usbd_xfer *xfer, *last; 704 705 if (xp->skip) { 706 /* 707 * Find the last transfer to skip, this is necessary 708 * as xhci_xfer_done() posts new transfers which we 709 * don't want to skip 710 */ 711 last = SIMPLEQ_FIRST(&xp->pipe.queue); 712 if (last == NULL) 713 goto done; 714 while ((xfer = SIMPLEQ_NEXT(last, next)) != NULL) 715 last = xfer; 716 717 do { 718 xfer = SIMPLEQ_FIRST(&xp->pipe.queue); 719 if (xfer == NULL) 720 goto done; 721 DPRINTF(("%s: skipping %p\n", __func__, xfer)); 722 xfer->status = USBD_NORMAL_COMPLETION; 723 xhci_xfer_done(xfer); 724 } while (xfer != last); 725 done: 726 xp->skip = 0; 727 } 728 } 729 730 void 731 xhci_event_xfer(struct xhci_softc *sc, uint64_t paddr, uint32_t status, 732 uint32_t flags) 733 { 734 struct xhci_pipe *xp; 735 struct usbd_xfer *xfer; 736 uint8_t dci, slot, code, xfertype; 737 uint32_t remain; 738 int trb_idx; 739 740 slot = XHCI_TRB_GET_SLOT(flags); 741 dci = XHCI_TRB_GET_EP(flags); 742 if (slot > sc->sc_noslot) { 743 DPRINTF(("%s: incorrect slot (%u)\n", DEVNAME(sc), slot)); 744 return; 745 } 746 747 xp = sc->sc_sdevs[slot].pipes[dci - 1]; 748 if (xp == NULL) { 749 DPRINTF(("%s: incorrect dci (%u)\n", DEVNAME(sc), dci)); 750 return; 751 } 752 753 code = XHCI_TRB_GET_CODE(status); 754 remain = XHCI_TRB_REMAIN(status); 755 756 switch (code) { 757 case XHCI_CODE_RING_UNDERRUN: 758 DPRINTF(("%s: slot %u underrun with %zu TRB\n", DEVNAME(sc), 759 slot, xp->ring.ntrb - xp->free_trbs)); 760 xhci_skip_all(xp); 761 return; 762 case XHCI_CODE_RING_OVERRUN: 763 DPRINTF(("%s: slot %u overrun with %zu TRB\n", DEVNAME(sc), 764 slot, xp->ring.ntrb - xp->free_trbs)); 765 xhci_skip_all(xp); 766 return; 767 case XHCI_CODE_MISSED_SRV: 768 DPRINTF(("%s: slot %u missed srv with %zu TRB\n", DEVNAME(sc), 769 slot, xp->ring.ntrb - xp->free_trbs)); 770 xp->skip = 1; 771 return; 772 default: 773 break; 774 } 775 776 trb_idx = (paddr - xp->ring.dma.paddr) / sizeof(struct xhci_trb); 777 if (trb_idx < 0 || trb_idx >= xp->ring.ntrb) { 778 printf("%s: wrong trb index (%u) max is %zu\n", DEVNAME(sc), 779 trb_idx, xp->ring.ntrb - 1); 780 return; 781 } 782 783 xfer = xp->pending_xfers[trb_idx]; 784 if (xfer == NULL) { 785 printf("%s: NULL xfer pointer\n", DEVNAME(sc)); 786 return; 787 } 788 789 if (remain > xfer->length) 790 remain = xfer->length; 791 792 xfertype = UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes); 793 794 switch (xfertype) { 795 case UE_BULK: 796 case UE_INTERRUPT: 797 case UE_CONTROL: 798 if (xhci_event_xfer_generic(sc, xfer, xp, remain, trb_idx, 799 code, slot, dci)) 800 return; 801 break; 802 case UE_ISOCHRONOUS: 803 if (xhci_event_xfer_isoc(xfer, xp, remain, trb_idx)) 804 return; 805 break; 806 default: 807 panic("xhci_event_xfer: unknown xfer type %u", xfertype); 808 } 809 810 xhci_xfer_done(xfer); 811 } 812 813 int 814 xhci_event_xfer_generic(struct xhci_softc *sc, struct usbd_xfer *xfer, 815 struct xhci_pipe *xp, uint32_t remain, int trb_idx, 816 uint8_t code, uint8_t slot, uint8_t dci) 817 { 818 struct xhci_xfer *xx = (struct xhci_xfer *)xfer; 819 820 switch (code) { 821 case XHCI_CODE_SUCCESS: 822 /* 823 * This might be the last TRB of a TD that ended up 824 * with a Short Transfer condition, see below. 825 */ 826 if (xfer->actlen == 0) 827 xfer->actlen = xfer->length - remain; 828 xfer->status = USBD_NORMAL_COMPLETION; 829 break; 830 case XHCI_CODE_SHORT_XFER: 831 xfer->actlen = xfer->length - remain; 832 /* 833 * If this is not the last TRB of a transfer, we should 834 * theoretically clear the IOC at the end of the chain 835 * but the HC might have already processed it before we 836 * had a chance to schedule the softinterrupt. 837 */ 838 if (xx->index != trb_idx) { 839 DPRINTF(("%s: short xfer %p for %u\n", 840 DEVNAME(sc), xfer, xx->index)); 841 return (1); 842 } 843 xfer->status = USBD_NORMAL_COMPLETION; 844 break; 845 case XHCI_CODE_TXERR: 846 case XHCI_CODE_SPLITERR: 847 DPRINTF(("%s: txerr? code %d\n", DEVNAME(sc), code)); 848 xfer->status = USBD_IOERROR; 849 break; 850 case XHCI_CODE_STALL: 851 case XHCI_CODE_BABBLE: 852 DPRINTF(("%s: babble code %d\n", DEVNAME(sc), code)); 853 /* Prevent any timeout to kick in. */ 854 timeout_del(&xfer->timeout_handle); 855 usb_rem_task(xfer->device, &xfer->abort_task); 856 857 /* We need to report this condition for umass(4). */ 858 if (code == XHCI_CODE_STALL) 859 xp->halted = USBD_STALLED; 860 else 861 xp->halted = USBD_IOERROR; 862 /* 863 * Since the stack might try to start a new transfer as 864 * soon as a pending one finishes, make sure the endpoint 865 * is fully reset before calling usb_transfer_complete(). 866 */ 867 xp->aborted_xfer = xfer; 868 xhci_cmd_reset_ep_async(sc, slot, dci); 869 return (1); 870 case XHCI_CODE_XFER_STOPPED: 871 case XHCI_CODE_XFER_STOPINV: 872 /* Endpoint stopped while processing a TD. */ 873 if (xfer == xp->aborted_xfer) { 874 DPRINTF(("%s: stopped xfer=%p\n", __func__, xfer)); 875 return (1); 876 } 877 878 /* FALLTHROUGH */ 879 default: 880 DPRINTF(("%s: unhandled code %d\n", DEVNAME(sc), code)); 881 xfer->status = USBD_IOERROR; 882 xp->halted = 1; 883 break; 884 } 885 886 return (0); 887 } 888 889 int 890 xhci_event_xfer_isoc(struct usbd_xfer *xfer, struct xhci_pipe *xp, 891 uint32_t remain, int trb_idx) 892 { 893 struct usbd_xfer *skipxfer; 894 struct xhci_xfer *xx = (struct xhci_xfer *)xfer; 895 int trb0_idx, frame_idx = 0; 896 897 KASSERT(xx->index >= 0); 898 trb0_idx = 899 ((xx->index + xp->ring.ntrb) - xx->ntrb) % (xp->ring.ntrb - 1); 900 901 /* Find the according frame index for this TRB. */ 902 while (trb0_idx != trb_idx) { 903 if ((xp->ring.trbs[trb0_idx].trb_flags & XHCI_TRB_TYPE_MASK) == 904 XHCI_TRB_TYPE_ISOCH) 905 frame_idx++; 906 if (trb0_idx++ == (xp->ring.ntrb - 1)) 907 trb0_idx = 0; 908 } 909 910 /* 911 * If we queued two TRBs for a frame and this is the second TRB, 912 * check if the first TRB needs accounting since it might not have 913 * raised an interrupt in case of full data received. 914 */ 915 if ((xp->ring.trbs[trb_idx].trb_flags & XHCI_TRB_TYPE_MASK) == 916 XHCI_TRB_TYPE_NORMAL) { 917 frame_idx--; 918 if (trb_idx == 0) 919 trb0_idx = xp->ring.ntrb - 2; 920 else 921 trb0_idx = trb_idx - 1; 922 if (xfer->frlengths[frame_idx] == 0) { 923 xfer->frlengths[frame_idx] = 924 XHCI_TRB_LEN(xp->ring.trbs[trb0_idx].trb_status); 925 } 926 } 927 928 xfer->frlengths[frame_idx] += 929 XHCI_TRB_LEN(xp->ring.trbs[trb_idx].trb_status) - remain; 930 xfer->actlen += xfer->frlengths[frame_idx]; 931 932 if (xx->index != trb_idx) 933 return (1); 934 935 if (xp->skip) { 936 while (1) { 937 skipxfer = SIMPLEQ_FIRST(&xp->pipe.queue); 938 if (skipxfer == xfer || skipxfer == NULL) 939 break; 940 DPRINTF(("%s: skipping %p\n", __func__, skipxfer)); 941 skipxfer->status = USBD_NORMAL_COMPLETION; 942 xhci_xfer_done(skipxfer); 943 } 944 xp->skip = 0; 945 } 946 947 xfer->status = USBD_NORMAL_COMPLETION; 948 949 return (0); 950 } 951 952 void 953 xhci_event_command(struct xhci_softc *sc, uint64_t paddr) 954 { 955 struct xhci_trb *trb; 956 struct xhci_pipe *xp; 957 uint32_t flags; 958 uint8_t dci, slot; 959 int trb_idx, status; 960 961 trb_idx = (paddr - sc->sc_cmd_ring.dma.paddr) / sizeof(*trb); 962 if (trb_idx < 0 || trb_idx >= sc->sc_cmd_ring.ntrb) { 963 printf("%s: wrong trb index (%u) max is %zu\n", DEVNAME(sc), 964 trb_idx, sc->sc_cmd_ring.ntrb - 1); 965 return; 966 } 967 968 trb = &sc->sc_cmd_ring.trbs[trb_idx]; 969 970 bus_dmamap_sync(sc->sc_cmd_ring.dma.tag, sc->sc_cmd_ring.dma.map, 971 TRBOFF(&sc->sc_cmd_ring, trb), sizeof(struct xhci_trb), 972 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 973 974 flags = letoh32(trb->trb_flags); 975 976 slot = XHCI_TRB_GET_SLOT(flags); 977 dci = XHCI_TRB_GET_EP(flags); 978 979 switch (flags & XHCI_TRB_TYPE_MASK) { 980 case XHCI_CMD_RESET_EP: 981 xp = sc->sc_sdevs[slot].pipes[dci - 1]; 982 if (xp == NULL) 983 break; 984 985 /* Update the dequeue pointer past the last TRB. */ 986 xhci_cmd_set_tr_deq_async(sc, xp->slot, xp->dci, 987 DEQPTR(xp->ring) | xp->ring.toggle); 988 break; 989 case XHCI_CMD_SET_TR_DEQ: 990 xp = sc->sc_sdevs[slot].pipes[dci - 1]; 991 if (xp == NULL) 992 break; 993 994 status = xp->halted; 995 xp->halted = 0; 996 if (xp->aborted_xfer != NULL) { 997 xp->aborted_xfer->status = status; 998 xhci_xfer_done(xp->aborted_xfer); 999 wakeup(xp); 1000 } 1001 break; 1002 case XHCI_CMD_CONFIG_EP: 1003 case XHCI_CMD_STOP_EP: 1004 case XHCI_CMD_DISABLE_SLOT: 1005 case XHCI_CMD_ENABLE_SLOT: 1006 case XHCI_CMD_ADDRESS_DEVICE: 1007 case XHCI_CMD_EVAL_CTX: 1008 case XHCI_CMD_NOOP: 1009 /* All these commands are synchronous. */ 1010 KASSERT(sc->sc_cmd_trb == trb); 1011 sc->sc_cmd_trb = NULL; 1012 wakeup(&sc->sc_cmd_trb); 1013 break; 1014 default: 1015 DPRINTF(("%s: unexpected command %x\n", DEVNAME(sc), flags)); 1016 } 1017 } 1018 1019 void 1020 xhci_event_port_change(struct xhci_softc *sc, uint64_t paddr, uint32_t status) 1021 { 1022 struct usbd_xfer *xfer = sc->sc_intrxfer; 1023 uint32_t port = XHCI_TRB_PORTID(paddr); 1024 uint8_t *p; 1025 1026 if (XHCI_TRB_GET_CODE(status) != XHCI_CODE_SUCCESS) { 1027 DPRINTF(("%s: failed port status event\n", DEVNAME(sc))); 1028 return; 1029 } 1030 1031 if (xfer == NULL) 1032 return; 1033 1034 p = KERNADDR(&xfer->dmabuf, 0); 1035 memset(p, 0, xfer->length); 1036 1037 p[port/8] |= 1 << (port%8); 1038 DPRINTF(("%s: port=%d change=0x%02x\n", DEVNAME(sc), port, *p)); 1039 1040 xfer->actlen = xfer->length; 1041 xfer->status = USBD_NORMAL_COMPLETION; 1042 1043 usb_transfer_complete(xfer); 1044 } 1045 1046 void 1047 xhci_xfer_done(struct usbd_xfer *xfer) 1048 { 1049 struct xhci_pipe *xp = (struct xhci_pipe *)xfer->pipe; 1050 struct xhci_xfer *xx = (struct xhci_xfer *)xfer; 1051 int ntrb, i; 1052 1053 splsoftassert(IPL_SOFTUSB); 1054 1055 #ifdef XHCI_DEBUG 1056 if (xx->index < 0 || xp->pending_xfers[xx->index] == NULL) { 1057 printf("%s: xfer=%p done (idx=%d, ntrb=%zd)\n", __func__, 1058 xfer, xx->index, xx->ntrb); 1059 } 1060 #endif 1061 1062 if (xp->aborted_xfer == xfer) 1063 xp->aborted_xfer = NULL; 1064 1065 for (ntrb = 0, i = xx->index; ntrb < xx->ntrb; ntrb++, i--) { 1066 xp->pending_xfers[i] = NULL; 1067 if (i == 0) 1068 i = (xp->ring.ntrb - 1); 1069 } 1070 xp->free_trbs += xx->ntrb; 1071 xx->index = -1; 1072 xx->ntrb = 0; 1073 1074 timeout_del(&xfer->timeout_handle); 1075 usb_rem_task(xfer->device, &xfer->abort_task); 1076 usb_transfer_complete(xfer); 1077 } 1078 1079 /* 1080 * Calculate the Device Context Index (DCI) for endpoints as stated 1081 * in section 4.5.1 of xHCI specification r1.1. 1082 */ 1083 static inline uint8_t 1084 xhci_ed2dci(usb_endpoint_descriptor_t *ed) 1085 { 1086 uint8_t dir; 1087 1088 if (UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) 1089 return (UE_GET_ADDR(ed->bEndpointAddress) * 2 + 1); 1090 1091 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 1092 dir = 1; 1093 else 1094 dir = 0; 1095 1096 return (UE_GET_ADDR(ed->bEndpointAddress) * 2 + dir); 1097 } 1098 1099 usbd_status 1100 xhci_pipe_open(struct usbd_pipe *pipe) 1101 { 1102 struct xhci_softc *sc = (struct xhci_softc *)pipe->device->bus; 1103 struct xhci_pipe *xp = (struct xhci_pipe *)pipe; 1104 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1105 uint8_t slot = 0, xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1106 int error; 1107 1108 KASSERT(xp->slot == 0); 1109 1110 if (sc->sc_bus.dying) 1111 return (USBD_IOERROR); 1112 1113 /* Root Hub */ 1114 if (pipe->device->depth == 0) { 1115 switch (ed->bEndpointAddress) { 1116 case USB_CONTROL_ENDPOINT: 1117 pipe->methods = &xhci_root_ctrl_methods; 1118 break; 1119 case UE_DIR_IN | XHCI_INTR_ENDPT: 1120 pipe->methods = &xhci_root_intr_methods; 1121 break; 1122 default: 1123 pipe->methods = NULL; 1124 return (USBD_INVAL); 1125 } 1126 return (USBD_NORMAL_COMPLETION); 1127 } 1128 1129 #if 0 1130 /* Issue a noop to check if the command ring is correctly configured. */ 1131 xhci_cmd_noop(sc); 1132 #endif 1133 1134 switch (xfertype) { 1135 case UE_CONTROL: 1136 pipe->methods = &xhci_device_ctrl_methods; 1137 1138 /* 1139 * Get a slot and init the device's contexts. 1140 * 1141 * Since the control enpoint, represented as the default 1142 * pipe, is always opened first we are dealing with a 1143 * new device. Put a new slot in the ENABLED state. 1144 * 1145 */ 1146 error = xhci_cmd_slot_control(sc, &slot, 1); 1147 if (error || slot == 0 || slot > sc->sc_noslot) 1148 return (USBD_INVAL); 1149 1150 if (xhci_softdev_alloc(sc, slot)) { 1151 xhci_cmd_slot_control(sc, &slot, 0); 1152 return (USBD_NOMEM); 1153 } 1154 1155 break; 1156 case UE_ISOCHRONOUS: 1157 pipe->methods = &xhci_device_isoc_methods; 1158 break; 1159 case UE_BULK: 1160 pipe->methods = &xhci_device_bulk_methods; 1161 break; 1162 case UE_INTERRUPT: 1163 pipe->methods = &xhci_device_intr_methods; 1164 break; 1165 default: 1166 return (USBD_INVAL); 1167 } 1168 1169 /* 1170 * Our USBD Bus Interface is pipe-oriented but for most of the 1171 * operations we need to access a device context, so keep track 1172 * of the slot ID in every pipe. 1173 */ 1174 if (slot == 0) 1175 slot = ((struct xhci_pipe *)pipe->device->default_pipe)->slot; 1176 1177 xp->slot = slot; 1178 xp->dci = xhci_ed2dci(ed); 1179 1180 if (xhci_pipe_init(sc, pipe)) { 1181 xhci_cmd_slot_control(sc, &slot, 0); 1182 return (USBD_IOERROR); 1183 } 1184 1185 return (USBD_NORMAL_COMPLETION); 1186 } 1187 1188 /* 1189 * Set the maximum Endpoint Service Interface Time (ESIT) payload and 1190 * the average TRB buffer length for an endpoint. 1191 */ 1192 static inline uint32_t 1193 xhci_get_txinfo(struct xhci_softc *sc, struct usbd_pipe *pipe) 1194 { 1195 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1196 uint32_t mep, atl, mps = UGETW(ed->wMaxPacketSize); 1197 1198 switch (ed->bmAttributes & UE_XFERTYPE) { 1199 case UE_CONTROL: 1200 mep = 0; 1201 atl = 8; 1202 break; 1203 case UE_INTERRUPT: 1204 case UE_ISOCHRONOUS: 1205 if (pipe->device->speed == USB_SPEED_SUPER) { 1206 /* XXX Read the companion descriptor */ 1207 } 1208 1209 mep = (UE_GET_TRANS(mps) + 1) * UE_GET_SIZE(mps); 1210 atl = mep; 1211 break; 1212 case UE_BULK: 1213 default: 1214 mep = 0; 1215 atl = 0; 1216 } 1217 1218 return (XHCI_EPCTX_MAX_ESIT_PAYLOAD(mep) | XHCI_EPCTX_AVG_TRB_LEN(atl)); 1219 } 1220 1221 static inline uint32_t 1222 xhci_linear_interval(usb_endpoint_descriptor_t *ed) 1223 { 1224 uint32_t ival = min(max(1, ed->bInterval), 255); 1225 1226 return (fls(ival) - 1); 1227 } 1228 1229 static inline uint32_t 1230 xhci_exponential_interval(usb_endpoint_descriptor_t *ed) 1231 { 1232 uint32_t ival = min(max(1, ed->bInterval), 16); 1233 1234 return (ival - 1); 1235 } 1236 /* 1237 * Return interval for endpoint expressed in 2^(ival) * 125us. 1238 * 1239 * See section 6.2.3.6 of xHCI r1.1 Specification for more details. 1240 */ 1241 uint32_t 1242 xhci_pipe_interval(struct usbd_pipe *pipe) 1243 { 1244 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1245 uint8_t speed = pipe->device->speed; 1246 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1247 uint32_t ival; 1248 1249 if (xfertype == UE_CONTROL || xfertype == UE_BULK) { 1250 /* Control and Bulk endpoints never NAKs. */ 1251 ival = 0; 1252 } else { 1253 switch (speed) { 1254 case USB_SPEED_FULL: 1255 if (xfertype == UE_ISOCHRONOUS) { 1256 /* Convert 1-2^(15)ms into 3-18 */ 1257 ival = xhci_exponential_interval(ed) + 3; 1258 break; 1259 } 1260 /* FALLTHROUGH */ 1261 case USB_SPEED_LOW: 1262 /* Convert 1-255ms into 3-10 */ 1263 ival = xhci_linear_interval(ed) + 3; 1264 break; 1265 case USB_SPEED_HIGH: 1266 case USB_SPEED_SUPER: 1267 default: 1268 /* Convert 1-2^(15) * 125us into 0-15 */ 1269 ival = xhci_exponential_interval(ed); 1270 break; 1271 } 1272 } 1273 1274 KASSERT(ival <= 15); 1275 return (XHCI_EPCTX_SET_IVAL(ival)); 1276 } 1277 1278 uint32_t 1279 xhci_pipe_maxburst(struct usbd_pipe *pipe) 1280 { 1281 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1282 uint32_t mps = UGETW(ed->wMaxPacketSize); 1283 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1284 uint32_t maxb = 0; 1285 1286 switch (pipe->device->speed) { 1287 case USB_SPEED_HIGH: 1288 if (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT) 1289 maxb = UE_GET_TRANS(mps); 1290 break; 1291 case USB_SPEED_SUPER: 1292 /* XXX Read the companion descriptor */ 1293 default: 1294 break; 1295 } 1296 1297 return (maxb); 1298 } 1299 1300 int 1301 xhci_context_setup(struct xhci_softc *sc, struct usbd_pipe *pipe) 1302 { 1303 struct xhci_pipe *xp = (struct xhci_pipe *)pipe; 1304 struct xhci_soft_dev *sdev = &sc->sc_sdevs[xp->slot]; 1305 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1306 uint32_t mps = UGETW(ed->wMaxPacketSize); 1307 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1308 uint8_t speed, cerr = 0; 1309 uint32_t route = 0, rhport = 0; 1310 struct usbd_device *hub; 1311 1312 /* 1313 * Calculate the Route String. Assume that there is no hub with 1314 * more than 15 ports and that they all have a detph < 6. See 1315 * section 8.9 of USB 3.1 Specification for more details. 1316 */ 1317 for (hub = pipe->device; hub->myhub->depth; hub = hub->myhub) { 1318 uint32_t port = hub->powersrc->portno; 1319 uint32_t depth = hub->myhub->depth; 1320 1321 route |= port << (4 * (depth - 1)); 1322 } 1323 1324 /* Get Root Hub port */ 1325 rhport = hub->powersrc->portno; 1326 1327 switch (pipe->device->speed) { 1328 case USB_SPEED_LOW: 1329 speed = XHCI_SPEED_LOW; 1330 break; 1331 case USB_SPEED_FULL: 1332 speed = XHCI_SPEED_FULL; 1333 break; 1334 case USB_SPEED_HIGH: 1335 speed = XHCI_SPEED_HIGH; 1336 break; 1337 case USB_SPEED_SUPER: 1338 speed = XHCI_SPEED_SUPER; 1339 break; 1340 default: 1341 return (USBD_INVAL); 1342 } 1343 1344 /* Setup the endpoint context */ 1345 if (xfertype != UE_ISOCHRONOUS) 1346 cerr = 3; 1347 1348 if ((ed->bEndpointAddress & UE_DIR_IN) || (xfertype == UE_CONTROL)) 1349 xfertype |= 0x4; 1350 1351 sdev->ep_ctx[xp->dci-1]->info_lo = htole32(xhci_pipe_interval(pipe)); 1352 sdev->ep_ctx[xp->dci-1]->info_hi = htole32( 1353 XHCI_EPCTX_SET_MPS(UE_GET_SIZE(mps)) | 1354 XHCI_EPCTX_SET_MAXB(xhci_pipe_maxburst(pipe)) | 1355 XHCI_EPCTX_SET_EPTYPE(xfertype) | XHCI_EPCTX_SET_CERR(cerr) 1356 ); 1357 sdev->ep_ctx[xp->dci-1]->txinfo = htole32(xhci_get_txinfo(sc, pipe)); 1358 sdev->ep_ctx[xp->dci-1]->deqp = htole64( 1359 DEQPTR(xp->ring) | xp->ring.toggle 1360 ); 1361 1362 /* Unmask the new endoint */ 1363 sdev->input_ctx->drop_flags = 0; 1364 sdev->input_ctx->add_flags = htole32(XHCI_INCTX_MASK_DCI(xp->dci)); 1365 1366 /* Setup the slot context */ 1367 sdev->slot_ctx->info_lo = htole32( 1368 XHCI_SCTX_DCI(xp->dci) | XHCI_SCTX_SPEED(speed) | 1369 XHCI_SCTX_ROUTE(route) 1370 ); 1371 sdev->slot_ctx->info_hi = htole32(XHCI_SCTX_RHPORT(rhport)); 1372 sdev->slot_ctx->tt = 0; 1373 sdev->slot_ctx->state = 0; 1374 1375 /* XXX */ 1376 #define UHUB_IS_MTT(dev) (dev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) 1377 /* 1378 * If we are opening the interrupt pipe of a hub, update its 1379 * context before putting it in the CONFIGURED state. 1380 */ 1381 if (pipe->device->hub != NULL) { 1382 int nports = pipe->device->hub->nports; 1383 1384 sdev->slot_ctx->info_lo |= htole32(XHCI_SCTX_HUB(1)); 1385 sdev->slot_ctx->info_hi |= htole32(XHCI_SCTX_NPORTS(nports)); 1386 1387 if (UHUB_IS_MTT(pipe->device)) 1388 sdev->slot_ctx->info_lo |= htole32(XHCI_SCTX_MTT(1)); 1389 1390 sdev->slot_ctx->tt |= htole32( 1391 XHCI_SCTX_TT_THINK_TIME(pipe->device->hub->ttthink) 1392 ); 1393 } 1394 1395 /* 1396 * If this is a Low or Full Speed device below an external High 1397 * Speed hub, it needs some TT love. 1398 */ 1399 if (speed < XHCI_SPEED_HIGH && pipe->device->myhsport != NULL) { 1400 struct usbd_device *hshub = pipe->device->myhsport->parent; 1401 uint8_t slot = ((struct xhci_pipe *)hshub->default_pipe)->slot; 1402 1403 if (UHUB_IS_MTT(hshub)) 1404 sdev->slot_ctx->info_lo |= htole32(XHCI_SCTX_MTT(1)); 1405 1406 sdev->slot_ctx->tt |= htole32( 1407 XHCI_SCTX_TT_HUB_SID(slot) | 1408 XHCI_SCTX_TT_PORT_NUM(pipe->device->myhsport->portno) 1409 ); 1410 } 1411 #undef UHUB_IS_MTT 1412 1413 /* Unmask the slot context */ 1414 sdev->input_ctx->add_flags |= htole32(XHCI_INCTX_MASK_DCI(0)); 1415 1416 bus_dmamap_sync(sdev->ictx_dma.tag, sdev->ictx_dma.map, 0, 1417 sc->sc_pagesize, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1418 1419 return (0); 1420 } 1421 1422 int 1423 xhci_pipe_init(struct xhci_softc *sc, struct usbd_pipe *pipe) 1424 { 1425 struct xhci_pipe *xp = (struct xhci_pipe *)pipe; 1426 struct xhci_soft_dev *sdev = &sc->sc_sdevs[xp->slot]; 1427 int error; 1428 1429 #ifdef XHCI_DEBUG 1430 struct usbd_device *dev = pipe->device; 1431 printf("%s: pipe=%p addr=%d depth=%d port=%d speed=%d dev %d dci %u" 1432 " (epAddr=0x%x)\n", __func__, pipe, dev->address, dev->depth, 1433 dev->powersrc->portno, dev->speed, xp->slot, xp->dci, 1434 pipe->endpoint->edesc->bEndpointAddress); 1435 #endif 1436 1437 if (xhci_ring_alloc(sc, &xp->ring, XHCI_MAX_XFER, XHCI_XFER_RING_ALIGN)) 1438 return (ENOMEM); 1439 1440 xp->free_trbs = xp->ring.ntrb; 1441 xp->halted = 0; 1442 1443 sdev->pipes[xp->dci - 1] = xp; 1444 1445 error = xhci_context_setup(sc, pipe); 1446 if (error) 1447 return (error); 1448 1449 if (xp->dci == 1) { 1450 /* 1451 * If we are opening the default pipe, the Slot should 1452 * be in the ENABLED state. Issue an "Address Device" 1453 * with BSR=1 to put the device in the DEFAULT state. 1454 * We cannot jump directly to the ADDRESSED state with 1455 * BSR=0 because some Low/Full speed devices won't accept 1456 * a SET_ADDRESS command before we've read their device 1457 * descriptor. 1458 */ 1459 error = xhci_cmd_set_address(sc, xp->slot, 1460 sdev->ictx_dma.paddr, XHCI_TRB_BSR); 1461 } else { 1462 error = xhci_cmd_configure_ep(sc, xp->slot, 1463 sdev->ictx_dma.paddr); 1464 } 1465 1466 if (error) { 1467 xhci_ring_free(sc, &xp->ring); 1468 return (EIO); 1469 } 1470 1471 return (0); 1472 } 1473 1474 void 1475 xhci_pipe_close(struct usbd_pipe *pipe) 1476 { 1477 struct xhci_softc *sc = (struct xhci_softc *)pipe->device->bus; 1478 struct xhci_pipe *lxp, *xp = (struct xhci_pipe *)pipe; 1479 struct xhci_soft_dev *sdev = &sc->sc_sdevs[xp->slot]; 1480 int i; 1481 1482 /* Root Hub */ 1483 if (pipe->device->depth == 0) 1484 return; 1485 1486 /* Mask the endpoint */ 1487 sdev->input_ctx->drop_flags = htole32(XHCI_INCTX_MASK_DCI(xp->dci)); 1488 sdev->input_ctx->add_flags = 0; 1489 1490 /* Update last valid Endpoint Context */ 1491 for (i = 30; i >= 0; i--) { 1492 lxp = sdev->pipes[i]; 1493 if (lxp != NULL && lxp != xp) 1494 break; 1495 } 1496 sdev->slot_ctx->info_lo = htole32(XHCI_SCTX_DCI(lxp->dci)); 1497 1498 /* Clear the Endpoint Context */ 1499 memset(sdev->ep_ctx[xp->dci - 1], 0, sizeof(struct xhci_epctx)); 1500 1501 bus_dmamap_sync(sdev->ictx_dma.tag, sdev->ictx_dma.map, 0, 1502 sc->sc_pagesize, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1503 1504 if (xhci_cmd_configure_ep(sc, xp->slot, sdev->ictx_dma.paddr)) 1505 DPRINTF(("%s: error clearing ep (%d)\n", DEVNAME(sc), xp->dci)); 1506 1507 xhci_ring_free(sc, &xp->ring); 1508 sdev->pipes[xp->dci - 1] = NULL; 1509 1510 /* 1511 * If we are closing the default pipe, the device is probably 1512 * gone, so put its slot in the DISABLED state. 1513 */ 1514 if (xp->dci == 1) { 1515 xhci_cmd_slot_control(sc, &xp->slot, 0); 1516 xhci_softdev_free(sc, xp->slot); 1517 } 1518 } 1519 1520 /* 1521 * Transition a device from DEFAULT to ADDRESSED Slot state, this hook 1522 * is needed for Low/Full speed devices. 1523 * 1524 * See section 4.5.3 of USB 3.1 Specification for more details. 1525 */ 1526 int 1527 xhci_setaddr(struct usbd_device *dev, int addr) 1528 { 1529 struct xhci_softc *sc = (struct xhci_softc *)dev->bus; 1530 struct xhci_pipe *xp = (struct xhci_pipe *)dev->default_pipe; 1531 struct xhci_soft_dev *sdev = &sc->sc_sdevs[xp->slot]; 1532 int error; 1533 1534 /* Root Hub */ 1535 if (dev->depth == 0) 1536 return (0); 1537 1538 KASSERT(xp->dci == 1); 1539 1540 error = xhci_context_setup(sc, dev->default_pipe); 1541 if (error) 1542 return (error); 1543 1544 error = xhci_cmd_set_address(sc, xp->slot, sdev->ictx_dma.paddr, 0); 1545 1546 #ifdef XHCI_DEBUG 1547 if (error == 0) { 1548 struct xhci_sctx *sctx; 1549 uint8_t addr; 1550 1551 bus_dmamap_sync(sdev->octx_dma.tag, sdev->octx_dma.map, 0, 1552 sc->sc_pagesize, BUS_DMASYNC_POSTREAD); 1553 1554 /* Get output slot context. */ 1555 sctx = (struct xhci_sctx *)sdev->octx_dma.vaddr; 1556 addr = XHCI_SCTX_DEV_ADDR(letoh32(sctx->state)); 1557 error = (addr == 0); 1558 1559 printf("%s: dev %d addr %d\n", DEVNAME(sc), xp->slot, addr); 1560 } 1561 #endif 1562 1563 return (error); 1564 } 1565 1566 struct usbd_xfer * 1567 xhci_allocx(struct usbd_bus *bus) 1568 { 1569 return (pool_get(xhcixfer, PR_NOWAIT | PR_ZERO)); 1570 } 1571 1572 void 1573 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1574 { 1575 pool_put(xhcixfer, xfer); 1576 } 1577 1578 int 1579 xhci_scratchpad_alloc(struct xhci_softc *sc, int npage) 1580 { 1581 uint64_t *pte; 1582 int error, i; 1583 1584 /* Allocate the required entry for the table. */ 1585 error = usbd_dma_contig_alloc(&sc->sc_bus, &sc->sc_spad.table_dma, 1586 (void **)&pte, npage * sizeof(uint64_t), XHCI_SPAD_TABLE_ALIGN, 1587 sc->sc_pagesize); 1588 if (error) 1589 return (ENOMEM); 1590 1591 /* Allocate pages. XXX does not need to be contiguous. */ 1592 error = usbd_dma_contig_alloc(&sc->sc_bus, &sc->sc_spad.pages_dma, 1593 NULL, npage * sc->sc_pagesize, sc->sc_pagesize, 0); 1594 if (error) { 1595 usbd_dma_contig_free(&sc->sc_bus, &sc->sc_spad.table_dma); 1596 return (ENOMEM); 1597 } 1598 1599 for (i = 0; i < npage; i++) { 1600 pte[i] = htole64( 1601 sc->sc_spad.pages_dma.paddr + (i * sc->sc_pagesize) 1602 ); 1603 } 1604 1605 bus_dmamap_sync(sc->sc_spad.table_dma.tag, sc->sc_spad.table_dma.map, 0, 1606 npage * sizeof(uint64_t), BUS_DMASYNC_PREREAD | 1607 BUS_DMASYNC_PREWRITE); 1608 1609 /* Entry 0 points to the table of scratchpad pointers. */ 1610 sc->sc_dcbaa.segs[0] = htole64(sc->sc_spad.table_dma.paddr); 1611 bus_dmamap_sync(sc->sc_dcbaa.dma.tag, sc->sc_dcbaa.dma.map, 0, 1612 sizeof(uint64_t), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1613 1614 sc->sc_spad.npage = npage; 1615 1616 return (0); 1617 } 1618 1619 void 1620 xhci_scratchpad_free(struct xhci_softc *sc) 1621 { 1622 sc->sc_dcbaa.segs[0] = 0; 1623 bus_dmamap_sync(sc->sc_dcbaa.dma.tag, sc->sc_dcbaa.dma.map, 0, 1624 sizeof(uint64_t), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1625 1626 usbd_dma_contig_free(&sc->sc_bus, &sc->sc_spad.pages_dma); 1627 usbd_dma_contig_free(&sc->sc_bus, &sc->sc_spad.table_dma); 1628 } 1629 1630 int 1631 xhci_ring_alloc(struct xhci_softc *sc, struct xhci_ring *ring, size_t ntrb, 1632 size_t alignment) 1633 { 1634 size_t size; 1635 int error; 1636 1637 size = ntrb * sizeof(struct xhci_trb); 1638 1639 error = usbd_dma_contig_alloc(&sc->sc_bus, &ring->dma, 1640 (void **)&ring->trbs, size, alignment, XHCI_RING_BOUNDARY); 1641 if (error) 1642 return (error); 1643 1644 ring->ntrb = ntrb; 1645 1646 xhci_ring_reset(sc, ring); 1647 1648 return (0); 1649 } 1650 1651 void 1652 xhci_ring_free(struct xhci_softc *sc, struct xhci_ring *ring) 1653 { 1654 usbd_dma_contig_free(&sc->sc_bus, &ring->dma); 1655 } 1656 1657 void 1658 xhci_ring_reset(struct xhci_softc *sc, struct xhci_ring *ring) 1659 { 1660 size_t size; 1661 1662 size = ring->ntrb * sizeof(struct xhci_trb); 1663 1664 memset(ring->trbs, 0, size); 1665 1666 ring->index = 0; 1667 ring->toggle = XHCI_TRB_CYCLE; 1668 1669 /* 1670 * Since all our rings use only one segment, at least for 1671 * the moment, link their tail to their head. 1672 */ 1673 if (ring != &sc->sc_evt_ring) { 1674 struct xhci_trb *trb = &ring->trbs[ring->ntrb - 1]; 1675 1676 trb->trb_paddr = htole64(ring->dma.paddr); 1677 trb->trb_flags = htole32(XHCI_TRB_TYPE_LINK | XHCI_TRB_LINKSEG | 1678 XHCI_TRB_CYCLE); 1679 bus_dmamap_sync(ring->dma.tag, ring->dma.map, 0, size, 1680 BUS_DMASYNC_PREWRITE); 1681 } else 1682 bus_dmamap_sync(ring->dma.tag, ring->dma.map, 0, size, 1683 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1684 } 1685 1686 struct xhci_trb* 1687 xhci_ring_consume(struct xhci_softc *sc, struct xhci_ring *ring) 1688 { 1689 struct xhci_trb *trb = &ring->trbs[ring->index]; 1690 1691 KASSERT(ring->index < ring->ntrb); 1692 1693 bus_dmamap_sync(ring->dma.tag, ring->dma.map, TRBOFF(ring, trb), 1694 sizeof(struct xhci_trb), BUS_DMASYNC_POSTREAD); 1695 1696 /* Make sure this TRB can be consumed. */ 1697 if (ring->toggle != (letoh32(trb->trb_flags) & XHCI_TRB_CYCLE)) 1698 return (NULL); 1699 1700 ring->index++; 1701 1702 if (ring->index == ring->ntrb) { 1703 ring->index = 0; 1704 ring->toggle ^= 1; 1705 } 1706 1707 return (trb); 1708 } 1709 1710 struct xhci_trb* 1711 xhci_ring_produce(struct xhci_softc *sc, struct xhci_ring *ring) 1712 { 1713 struct xhci_trb *lnk, *trb; 1714 1715 KASSERT(ring->index < ring->ntrb); 1716 1717 /* Setup the link TRB after the previous TRB is done. */ 1718 if (ring->index == 0) { 1719 lnk = &ring->trbs[ring->ntrb - 1]; 1720 trb = &ring->trbs[ring->ntrb - 2]; 1721 1722 bus_dmamap_sync(ring->dma.tag, ring->dma.map, TRBOFF(ring, lnk), 1723 sizeof(struct xhci_trb), BUS_DMASYNC_POSTREAD | 1724 BUS_DMASYNC_POSTWRITE); 1725 1726 lnk->trb_flags &= htole32(~XHCI_TRB_CHAIN); 1727 if (letoh32(trb->trb_flags) & XHCI_TRB_CHAIN) 1728 lnk->trb_flags |= htole32(XHCI_TRB_CHAIN); 1729 1730 bus_dmamap_sync(ring->dma.tag, ring->dma.map, TRBOFF(ring, lnk), 1731 sizeof(struct xhci_trb), BUS_DMASYNC_PREWRITE); 1732 1733 lnk->trb_flags ^= htole32(XHCI_TRB_CYCLE); 1734 1735 bus_dmamap_sync(ring->dma.tag, ring->dma.map, TRBOFF(ring, lnk), 1736 sizeof(struct xhci_trb), BUS_DMASYNC_PREWRITE); 1737 } 1738 1739 trb = &ring->trbs[ring->index++]; 1740 bus_dmamap_sync(ring->dma.tag, ring->dma.map, TRBOFF(ring, trb), 1741 sizeof(struct xhci_trb), BUS_DMASYNC_POSTREAD | 1742 BUS_DMASYNC_POSTWRITE); 1743 1744 /* Toggle cycle state of the link TRB and skip it. */ 1745 if (ring->index == (ring->ntrb - 1)) { 1746 ring->index = 0; 1747 ring->toggle ^= 1; 1748 } 1749 1750 return (trb); 1751 } 1752 1753 struct xhci_trb * 1754 xhci_xfer_get_trb(struct xhci_softc *sc, struct usbd_xfer *xfer, 1755 uint8_t *togglep, int last) 1756 { 1757 struct xhci_pipe *xp = (struct xhci_pipe *)xfer->pipe; 1758 struct xhci_xfer *xx = (struct xhci_xfer *)xfer; 1759 1760 KASSERT(xp->free_trbs >= 1); 1761 1762 /* Associate this TRB to our xfer. */ 1763 xp->pending_xfers[xp->ring.index] = xfer; 1764 xp->free_trbs--; 1765 1766 xx->index = (last) ? xp->ring.index : -2; 1767 xx->ntrb += 1; 1768 1769 *togglep = xp->ring.toggle; 1770 return (xhci_ring_produce(sc, &xp->ring)); 1771 } 1772 1773 int 1774 xhci_command_submit(struct xhci_softc *sc, struct xhci_trb *trb0, int timeout) 1775 { 1776 struct xhci_trb *trb; 1777 int s, error = 0; 1778 1779 KASSERT(timeout == 0 || sc->sc_cmd_trb == NULL); 1780 1781 trb0->trb_flags |= htole32(sc->sc_cmd_ring.toggle); 1782 1783 trb = xhci_ring_produce(sc, &sc->sc_cmd_ring); 1784 if (trb == NULL) 1785 return (EAGAIN); 1786 trb->trb_paddr = trb0->trb_paddr; 1787 trb->trb_status = trb0->trb_status; 1788 bus_dmamap_sync(sc->sc_cmd_ring.dma.tag, sc->sc_cmd_ring.dma.map, 1789 TRBOFF(&sc->sc_cmd_ring, trb), sizeof(struct xhci_trb), 1790 BUS_DMASYNC_PREWRITE); 1791 1792 trb->trb_flags = trb0->trb_flags; 1793 bus_dmamap_sync(sc->sc_cmd_ring.dma.tag, sc->sc_cmd_ring.dma.map, 1794 TRBOFF(&sc->sc_cmd_ring, trb), sizeof(struct xhci_trb), 1795 BUS_DMASYNC_PREWRITE); 1796 1797 if (timeout == 0) { 1798 XDWRITE4(sc, XHCI_DOORBELL(0), 0); 1799 return (0); 1800 } 1801 1802 rw_assert_wrlock(&sc->sc_cmd_lock); 1803 1804 s = splusb(); 1805 sc->sc_cmd_trb = trb; 1806 XDWRITE4(sc, XHCI_DOORBELL(0), 0); 1807 error = tsleep(&sc->sc_cmd_trb, PZERO, "xhcicmd", 1808 (timeout*hz+999)/ 1000 + 1); 1809 if (error) { 1810 #ifdef XHCI_DEBUG 1811 printf("%s: tsleep() = %d\n", __func__, error); 1812 printf("cmd = %d ", XHCI_TRB_TYPE(letoh32(trb->trb_flags))); 1813 xhci_dump_trb(trb); 1814 #endif 1815 KASSERT(sc->sc_cmd_trb == trb); 1816 sc->sc_cmd_trb = NULL; 1817 splx(s); 1818 return (error); 1819 } 1820 splx(s); 1821 1822 memcpy(trb0, &sc->sc_result_trb, sizeof(struct xhci_trb)); 1823 1824 if (XHCI_TRB_GET_CODE(letoh32(trb0->trb_status)) == XHCI_CODE_SUCCESS) 1825 return (0); 1826 1827 #ifdef XHCI_DEBUG 1828 printf("%s: event error code=%d, result=%d \n", DEVNAME(sc), 1829 XHCI_TRB_GET_CODE(letoh32(trb0->trb_status)), 1830 XHCI_TRB_TYPE(letoh32(trb0->trb_flags))); 1831 xhci_dump_trb(trb0); 1832 #endif 1833 return (EIO); 1834 } 1835 1836 int 1837 xhci_command_abort(struct xhci_softc *sc) 1838 { 1839 uint32_t reg; 1840 int i; 1841 1842 reg = XOREAD4(sc, XHCI_CRCR_LO); 1843 if ((reg & XHCI_CRCR_LO_CRR) == 0) 1844 return (0); 1845 1846 XOWRITE4(sc, XHCI_CRCR_LO, reg | XHCI_CRCR_LO_CA); 1847 XOWRITE4(sc, XHCI_CRCR_HI, 0); 1848 1849 for (i = 0; i < 250; i++) { 1850 usb_delay_ms(&sc->sc_bus, 1); 1851 reg = XOREAD4(sc, XHCI_CRCR_LO) & XHCI_CRCR_LO_CRR; 1852 if (!reg) 1853 break; 1854 } 1855 1856 if (reg) { 1857 printf("%s: command ring abort timeout\n", DEVNAME(sc)); 1858 return (1); 1859 } 1860 1861 return (0); 1862 } 1863 1864 int 1865 xhci_cmd_configure_ep(struct xhci_softc *sc, uint8_t slot, uint64_t addr) 1866 { 1867 struct xhci_trb trb; 1868 int error; 1869 1870 DPRINTF(("%s: %s dev %u\n", DEVNAME(sc), __func__, slot)); 1871 1872 trb.trb_paddr = htole64(addr); 1873 trb.trb_status = 0; 1874 trb.trb_flags = htole32( 1875 XHCI_TRB_SET_SLOT(slot) | XHCI_CMD_CONFIG_EP 1876 ); 1877 1878 rw_enter_write(&sc->sc_cmd_lock); 1879 error = xhci_command_submit(sc, &trb, XHCI_CMD_TIMEOUT); 1880 rw_exit_write(&sc->sc_cmd_lock); 1881 return (error); 1882 } 1883 1884 int 1885 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t slot, uint8_t dci) 1886 { 1887 struct xhci_trb trb; 1888 int error; 1889 1890 DPRINTF(("%s: %s dev %u dci %u\n", DEVNAME(sc), __func__, slot, dci)); 1891 1892 trb.trb_paddr = 0; 1893 trb.trb_status = 0; 1894 trb.trb_flags = htole32( 1895 XHCI_TRB_SET_SLOT(slot) | XHCI_TRB_SET_EP(dci) | XHCI_CMD_STOP_EP 1896 ); 1897 1898 rw_enter_write(&sc->sc_cmd_lock); 1899 error = xhci_command_submit(sc, &trb, XHCI_CMD_TIMEOUT); 1900 rw_exit_write(&sc->sc_cmd_lock); 1901 return (error); 1902 } 1903 1904 void 1905 xhci_cmd_reset_ep_async(struct xhci_softc *sc, uint8_t slot, uint8_t dci) 1906 { 1907 struct xhci_trb trb; 1908 1909 DPRINTF(("%s: %s dev %u dci %u\n", DEVNAME(sc), __func__, slot, dci)); 1910 1911 trb.trb_paddr = 0; 1912 trb.trb_status = 0; 1913 trb.trb_flags = htole32( 1914 XHCI_TRB_SET_SLOT(slot) | XHCI_TRB_SET_EP(dci) | XHCI_CMD_RESET_EP 1915 ); 1916 1917 xhci_command_submit(sc, &trb, 0); 1918 } 1919 1920 void 1921 xhci_cmd_set_tr_deq_async(struct xhci_softc *sc, uint8_t slot, uint8_t dci, 1922 uint64_t addr) 1923 { 1924 struct xhci_trb trb; 1925 1926 DPRINTF(("%s: %s dev %u dci %u\n", DEVNAME(sc), __func__, slot, dci)); 1927 1928 trb.trb_paddr = htole64(addr); 1929 trb.trb_status = 0; 1930 trb.trb_flags = htole32( 1931 XHCI_TRB_SET_SLOT(slot) | XHCI_TRB_SET_EP(dci) | XHCI_CMD_SET_TR_DEQ 1932 ); 1933 1934 xhci_command_submit(sc, &trb, 0); 1935 } 1936 1937 int 1938 xhci_cmd_slot_control(struct xhci_softc *sc, uint8_t *slotp, int enable) 1939 { 1940 struct xhci_trb trb; 1941 int error; 1942 1943 DPRINTF(("%s: %s\n", DEVNAME(sc), __func__)); 1944 1945 trb.trb_paddr = 0; 1946 trb.trb_status = 0; 1947 if (enable) 1948 trb.trb_flags = htole32(XHCI_CMD_ENABLE_SLOT); 1949 else 1950 trb.trb_flags = htole32( 1951 XHCI_TRB_SET_SLOT(*slotp) | XHCI_CMD_DISABLE_SLOT 1952 ); 1953 1954 rw_enter_write(&sc->sc_cmd_lock); 1955 error = xhci_command_submit(sc, &trb, XHCI_CMD_TIMEOUT); 1956 rw_exit_write(&sc->sc_cmd_lock); 1957 if (error != 0) 1958 return (EIO); 1959 1960 if (enable) 1961 *slotp = XHCI_TRB_GET_SLOT(letoh32(trb.trb_flags)); 1962 1963 return (0); 1964 } 1965 1966 int 1967 xhci_cmd_set_address(struct xhci_softc *sc, uint8_t slot, uint64_t addr, 1968 uint32_t bsr) 1969 { 1970 struct xhci_trb trb; 1971 int error; 1972 1973 DPRINTF(("%s: %s BSR=%u\n", DEVNAME(sc), __func__, bsr ? 1 : 0)); 1974 1975 trb.trb_paddr = htole64(addr); 1976 trb.trb_status = 0; 1977 trb.trb_flags = htole32( 1978 XHCI_TRB_SET_SLOT(slot) | XHCI_CMD_ADDRESS_DEVICE | bsr 1979 ); 1980 1981 rw_enter_write(&sc->sc_cmd_lock); 1982 error = xhci_command_submit(sc, &trb, XHCI_CMD_TIMEOUT); 1983 rw_exit_write(&sc->sc_cmd_lock); 1984 return (error); 1985 } 1986 1987 int 1988 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint8_t slot, uint64_t addr) 1989 { 1990 struct xhci_trb trb; 1991 int error; 1992 1993 DPRINTF(("%s: %s dev %u\n", DEVNAME(sc), __func__, slot)); 1994 1995 trb.trb_paddr = htole64(addr); 1996 trb.trb_status = 0; 1997 trb.trb_flags = htole32( 1998 XHCI_TRB_SET_SLOT(slot) | XHCI_CMD_EVAL_CTX 1999 ); 2000 2001 rw_enter_write(&sc->sc_cmd_lock); 2002 error = xhci_command_submit(sc, &trb, XHCI_CMD_TIMEOUT); 2003 rw_exit_write(&sc->sc_cmd_lock); 2004 return (error); 2005 } 2006 2007 #ifdef XHCI_DEBUG 2008 int 2009 xhci_cmd_noop(struct xhci_softc *sc) 2010 { 2011 struct xhci_trb trb; 2012 int error; 2013 2014 DPRINTF(("%s: %s\n", DEVNAME(sc), __func__)); 2015 2016 trb.trb_paddr = 0; 2017 trb.trb_status = 0; 2018 trb.trb_flags = htole32(XHCI_CMD_NOOP); 2019 2020 rw_enter_write(&sc->sc_cmd_lock); 2021 error = xhci_command_submit(sc, &trb, XHCI_CMD_TIMEOUT); 2022 rw_exit_write(&sc->sc_cmd_lock); 2023 return (error); 2024 } 2025 #endif 2026 2027 int 2028 xhci_softdev_alloc(struct xhci_softc *sc, uint8_t slot) 2029 { 2030 struct xhci_soft_dev *sdev = &sc->sc_sdevs[slot]; 2031 int i, error; 2032 uint8_t *kva; 2033 2034 /* 2035 * Setup input context. Even with 64 byte context size, it 2036 * fits into the smallest supported page size, so use that. 2037 */ 2038 error = usbd_dma_contig_alloc(&sc->sc_bus, &sdev->ictx_dma, 2039 (void **)&kva, sc->sc_pagesize, XHCI_ICTX_ALIGN, sc->sc_pagesize); 2040 if (error) 2041 return (ENOMEM); 2042 2043 sdev->input_ctx = (struct xhci_inctx *)kva; 2044 sdev->slot_ctx = (struct xhci_sctx *)(kva + sc->sc_ctxsize); 2045 for (i = 0; i < 31; i++) 2046 sdev->ep_ctx[i] = 2047 (struct xhci_epctx *)(kva + (i + 2) * sc->sc_ctxsize); 2048 2049 DPRINTF(("%s: dev %d, input=%p slot=%p ep0=%p\n", DEVNAME(sc), 2050 slot, sdev->input_ctx, sdev->slot_ctx, sdev->ep_ctx[0])); 2051 2052 /* Setup output context */ 2053 error = usbd_dma_contig_alloc(&sc->sc_bus, &sdev->octx_dma, NULL, 2054 sc->sc_pagesize, XHCI_OCTX_ALIGN, sc->sc_pagesize); 2055 if (error) { 2056 usbd_dma_contig_free(&sc->sc_bus, &sdev->ictx_dma); 2057 return (ENOMEM); 2058 } 2059 2060 memset(&sdev->pipes, 0, sizeof(sdev->pipes)); 2061 2062 DPRINTF(("%s: dev %d, setting DCBAA to 0x%016llx\n", DEVNAME(sc), 2063 slot, (long long)sdev->octx_dma.paddr)); 2064 2065 sc->sc_dcbaa.segs[slot] = htole64(sdev->octx_dma.paddr); 2066 bus_dmamap_sync(sc->sc_dcbaa.dma.tag, sc->sc_dcbaa.dma.map, 2067 slot * sizeof(uint64_t), sizeof(uint64_t), BUS_DMASYNC_PREREAD | 2068 BUS_DMASYNC_PREWRITE); 2069 2070 return (0); 2071 } 2072 2073 void 2074 xhci_softdev_free(struct xhci_softc *sc, uint8_t slot) 2075 { 2076 struct xhci_soft_dev *sdev = &sc->sc_sdevs[slot]; 2077 2078 sc->sc_dcbaa.segs[slot] = 0; 2079 bus_dmamap_sync(sc->sc_dcbaa.dma.tag, sc->sc_dcbaa.dma.map, 2080 slot * sizeof(uint64_t), sizeof(uint64_t), BUS_DMASYNC_PREREAD | 2081 BUS_DMASYNC_PREWRITE); 2082 2083 usbd_dma_contig_free(&sc->sc_bus, &sdev->octx_dma); 2084 usbd_dma_contig_free(&sc->sc_bus, &sdev->ictx_dma); 2085 2086 memset(sdev, 0, sizeof(struct xhci_soft_dev)); 2087 } 2088 2089 /* Root hub descriptors. */ 2090 usb_device_descriptor_t xhci_devd = { 2091 USB_DEVICE_DESCRIPTOR_SIZE, 2092 UDESC_DEVICE, /* type */ 2093 {0x00, 0x03}, /* USB version */ 2094 UDCLASS_HUB, /* class */ 2095 UDSUBCLASS_HUB, /* subclass */ 2096 UDPROTO_HSHUBSTT, /* protocol */ 2097 9, /* max packet */ 2098 {0},{0},{0x00,0x01}, /* device id */ 2099 1,2,0, /* string indexes */ 2100 1 /* # of configurations */ 2101 }; 2102 2103 const usb_config_descriptor_t xhci_confd = { 2104 USB_CONFIG_DESCRIPTOR_SIZE, 2105 UDESC_CONFIG, 2106 {USB_CONFIG_DESCRIPTOR_SIZE + 2107 USB_INTERFACE_DESCRIPTOR_SIZE + 2108 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2109 1, 2110 1, 2111 0, 2112 UC_BUS_POWERED | UC_SELF_POWERED, 2113 0 /* max power */ 2114 }; 2115 2116 const usb_interface_descriptor_t xhci_ifcd = { 2117 USB_INTERFACE_DESCRIPTOR_SIZE, 2118 UDESC_INTERFACE, 2119 0, 2120 0, 2121 1, 2122 UICLASS_HUB, 2123 UISUBCLASS_HUB, 2124 UIPROTO_HSHUBSTT, 2125 0 2126 }; 2127 2128 const usb_endpoint_descriptor_t xhci_endpd = { 2129 USB_ENDPOINT_DESCRIPTOR_SIZE, 2130 UDESC_ENDPOINT, 2131 UE_DIR_IN | XHCI_INTR_ENDPT, 2132 UE_INTERRUPT, 2133 {2, 0}, /* max 15 ports */ 2134 255 2135 }; 2136 2137 const usb_endpoint_ss_comp_descriptor_t xhci_endpcd = { 2138 USB_ENDPOINT_SS_COMP_DESCRIPTOR_SIZE, 2139 UDESC_ENDPOINT_SS_COMP, 2140 0, 2141 0, 2142 {0, 0} 2143 }; 2144 2145 const usb_hub_descriptor_t xhci_hubd = { 2146 USB_HUB_DESCRIPTOR_SIZE, 2147 UDESC_SS_HUB, 2148 0, 2149 {0,0}, 2150 0, 2151 0, 2152 {0}, 2153 }; 2154 2155 void 2156 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2157 { 2158 struct xhci_softc *sc = (struct xhci_softc *)xfer->device->bus; 2159 struct xhci_pipe *xp = (struct xhci_pipe *)xfer->pipe; 2160 int error; 2161 2162 splsoftassert(IPL_SOFTUSB); 2163 2164 DPRINTF(("%s: xfer=%p status=%s err=%s actlen=%d len=%d idx=%d\n", 2165 __func__, xfer, usbd_errstr(xfer->status), usbd_errstr(status), 2166 xfer->actlen, xfer->length, ((struct xhci_xfer *)xfer)->index)); 2167 2168 /* XXX The stack should not call abort() in this case. */ 2169 if (sc->sc_bus.dying || xfer->status == USBD_NOT_STARTED) { 2170 xfer->status = status; 2171 timeout_del(&xfer->timeout_handle); 2172 usb_rem_task(xfer->device, &xfer->abort_task); 2173 usb_transfer_complete(xfer); 2174 return; 2175 } 2176 2177 /* Transfer is already done. */ 2178 if (xfer->status != USBD_IN_PROGRESS) { 2179 DPRINTF(("%s: already done \n", __func__)); 2180 return; 2181 } 2182 2183 /* Prevent any timeout to kick in. */ 2184 timeout_del(&xfer->timeout_handle); 2185 usb_rem_task(xfer->device, &xfer->abort_task); 2186 2187 /* Indicate that we are aborting this transfer. */ 2188 xp->halted = status; 2189 xp->aborted_xfer = xfer; 2190 2191 /* Stop the endpoint and wait until the hardware says so. */ 2192 if (xhci_cmd_stop_ep(sc, xp->slot, xp->dci)) { 2193 DPRINTF(("%s: error stopping endpoint\n", DEVNAME(sc))); 2194 /* Assume the device is gone. */ 2195 xp->halted = 0; 2196 xp->aborted_xfer = NULL; 2197 xfer->status = status; 2198 usb_transfer_complete(xfer); 2199 return; 2200 } 2201 2202 /* 2203 * The transfer was already completed when we stopped the 2204 * endpoint, no need to move the dequeue pointer past its 2205 * TRBs. 2206 */ 2207 if (xp->aborted_xfer == NULL) { 2208 DPRINTF(("%s: done before stopping the endpoint\n", __func__)); 2209 xp->halted = 0; 2210 return; 2211 } 2212 2213 /* 2214 * At this stage the endpoint has been stopped, so update its 2215 * dequeue pointer past the last TRB of the transfer. 2216 * 2217 * Note: This assumes that only one transfer per endpoint has 2218 * pending TRBs on the ring. 2219 */ 2220 xhci_cmd_set_tr_deq_async(sc, xp->slot, xp->dci, 2221 DEQPTR(xp->ring) | xp->ring.toggle); 2222 error = tsleep(xp, PZERO, "xhciab", (XHCI_CMD_TIMEOUT*hz+999)/1000 + 1); 2223 if (error) 2224 printf("%s: timeout aborting transfer\n", DEVNAME(sc)); 2225 } 2226 2227 void 2228 xhci_timeout(void *addr) 2229 { 2230 struct usbd_xfer *xfer = addr; 2231 struct xhci_softc *sc = (struct xhci_softc *)xfer->device->bus; 2232 2233 if (sc->sc_bus.dying) { 2234 xhci_timeout_task(addr); 2235 return; 2236 } 2237 2238 usb_init_task(&xfer->abort_task, xhci_timeout_task, addr, 2239 USB_TASK_TYPE_ABORT); 2240 usb_add_task(xfer->device, &xfer->abort_task); 2241 } 2242 2243 void 2244 xhci_timeout_task(void *addr) 2245 { 2246 struct usbd_xfer *xfer = addr; 2247 int s; 2248 2249 s = splusb(); 2250 xhci_abort_xfer(xfer, USBD_TIMEOUT); 2251 splx(s); 2252 } 2253 2254 usbd_status 2255 xhci_root_ctrl_transfer(struct usbd_xfer *xfer) 2256 { 2257 usbd_status err; 2258 2259 err = usb_insert_transfer(xfer); 2260 if (err) 2261 return (err); 2262 2263 return (xhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2264 } 2265 2266 usbd_status 2267 xhci_root_ctrl_start(struct usbd_xfer *xfer) 2268 { 2269 struct xhci_softc *sc = (struct xhci_softc *)xfer->device->bus; 2270 usb_port_status_t ps; 2271 usb_device_request_t *req; 2272 void *buf = NULL; 2273 usb_hub_descriptor_t hubd; 2274 usbd_status err; 2275 int s, len, value, index; 2276 int l, totlen = 0; 2277 int port, i; 2278 uint32_t v; 2279 2280 KASSERT(xfer->rqflags & URQ_REQUEST); 2281 2282 if (sc->sc_bus.dying) 2283 return (USBD_IOERROR); 2284 2285 req = &xfer->request; 2286 2287 DPRINTFN(4,("%s: type=0x%02x request=%02x\n", __func__, 2288 req->bmRequestType, req->bRequest)); 2289 2290 len = UGETW(req->wLength); 2291 value = UGETW(req->wValue); 2292 index = UGETW(req->wIndex); 2293 2294 if (len != 0) 2295 buf = KERNADDR(&xfer->dmabuf, 0); 2296 2297 #define C(x,y) ((x) | ((y) << 8)) 2298 switch(C(req->bRequest, req->bmRequestType)) { 2299 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2300 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2301 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2302 /* 2303 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2304 * for the integrated root hub. 2305 */ 2306 break; 2307 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2308 if (len > 0) { 2309 *(uint8_t *)buf = sc->sc_conf; 2310 totlen = 1; 2311 } 2312 break; 2313 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2314 DPRINTFN(8,("xhci_root_ctrl_start: wValue=0x%04x\n", value)); 2315 switch(value >> 8) { 2316 case UDESC_DEVICE: 2317 if ((value & 0xff) != 0) { 2318 err = USBD_IOERROR; 2319 goto ret; 2320 } 2321 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2322 USETW(xhci_devd.idVendor, sc->sc_id_vendor); 2323 memcpy(buf, &xhci_devd, l); 2324 break; 2325 /* 2326 * We can't really operate at another speed, but the spec says 2327 * we need this descriptor. 2328 */ 2329 case UDESC_OTHER_SPEED_CONFIGURATION: 2330 case UDESC_CONFIG: 2331 if ((value & 0xff) != 0) { 2332 err = USBD_IOERROR; 2333 goto ret; 2334 } 2335 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2336 memcpy(buf, &xhci_confd, l); 2337 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2338 value >> 8; 2339 buf = (char *)buf + l; 2340 len -= l; 2341 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2342 totlen += l; 2343 memcpy(buf, &xhci_ifcd, l); 2344 buf = (char *)buf + l; 2345 len -= l; 2346 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2347 totlen += l; 2348 memcpy(buf, &xhci_endpd, l); 2349 break; 2350 case UDESC_STRING: 2351 if (len == 0) 2352 break; 2353 *(u_int8_t *)buf = 0; 2354 totlen = 1; 2355 switch (value & 0xff) { 2356 case 0: /* Language table */ 2357 totlen = usbd_str(buf, len, "\001"); 2358 break; 2359 case 1: /* Vendor */ 2360 totlen = usbd_str(buf, len, sc->sc_vendor); 2361 break; 2362 case 2: /* Product */ 2363 totlen = usbd_str(buf, len, "xHCI root hub"); 2364 break; 2365 } 2366 break; 2367 default: 2368 err = USBD_IOERROR; 2369 goto ret; 2370 } 2371 break; 2372 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2373 if (len > 0) { 2374 *(uint8_t *)buf = 0; 2375 totlen = 1; 2376 } 2377 break; 2378 case C(UR_GET_STATUS, UT_READ_DEVICE): 2379 if (len > 1) { 2380 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2381 totlen = 2; 2382 } 2383 break; 2384 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2385 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2386 if (len > 1) { 2387 USETW(((usb_status_t *)buf)->wStatus, 0); 2388 totlen = 2; 2389 } 2390 break; 2391 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2392 if (value >= USB_MAX_DEVICES) { 2393 err = USBD_IOERROR; 2394 goto ret; 2395 } 2396 break; 2397 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2398 if (value != 0 && value != 1) { 2399 err = USBD_IOERROR; 2400 goto ret; 2401 } 2402 sc->sc_conf = value; 2403 break; 2404 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2405 break; 2406 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2407 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2408 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2409 err = USBD_IOERROR; 2410 goto ret; 2411 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2412 break; 2413 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2414 break; 2415 /* Hub requests */ 2416 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2417 break; 2418 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2419 DPRINTFN(8, ("xhci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2420 "port=%d feature=%d\n", index, value)); 2421 if (index < 1 || index > sc->sc_noport) { 2422 err = USBD_IOERROR; 2423 goto ret; 2424 } 2425 port = XHCI_PORTSC(index); 2426 v = XOREAD4(sc, port) & ~XHCI_PS_CLEAR; 2427 switch (value) { 2428 case UHF_PORT_ENABLE: 2429 XOWRITE4(sc, port, v | XHCI_PS_PED); 2430 break; 2431 case UHF_PORT_SUSPEND: 2432 /* TODO */ 2433 break; 2434 case UHF_PORT_POWER: 2435 XOWRITE4(sc, port, v & ~XHCI_PS_PP); 2436 break; 2437 case UHF_PORT_INDICATOR: 2438 XOWRITE4(sc, port, v & ~XHCI_PS_SET_PIC(3)); 2439 break; 2440 case UHF_C_PORT_CONNECTION: 2441 XOWRITE4(sc, port, v | XHCI_PS_CSC); 2442 break; 2443 case UHF_C_PORT_ENABLE: 2444 XOWRITE4(sc, port, v | XHCI_PS_PEC); 2445 break; 2446 case UHF_C_PORT_SUSPEND: 2447 case UHF_C_PORT_LINK_STATE: 2448 XOWRITE4(sc, port, v | XHCI_PS_PLC); 2449 break; 2450 case UHF_C_PORT_OVER_CURRENT: 2451 XOWRITE4(sc, port, v | XHCI_PS_OCC); 2452 break; 2453 case UHF_C_PORT_RESET: 2454 XOWRITE4(sc, port, v | XHCI_PS_PRC); 2455 break; 2456 case UHF_C_BH_PORT_RESET: 2457 XOWRITE4(sc, port, v | XHCI_PS_WRC); 2458 break; 2459 default: 2460 err = USBD_IOERROR; 2461 goto ret; 2462 } 2463 break; 2464 2465 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2466 if (len == 0) 2467 break; 2468 if ((value & 0xff) != 0) { 2469 err = USBD_IOERROR; 2470 goto ret; 2471 } 2472 v = XREAD4(sc, XHCI_HCCPARAMS); 2473 hubd = xhci_hubd; 2474 hubd.bNbrPorts = sc->sc_noport; 2475 USETW(hubd.wHubCharacteristics, 2476 (XHCI_HCC_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_GANGED) | 2477 (XHCI_HCC_PIND(v) ? UHD_PORT_IND : 0)); 2478 hubd.bPwrOn2PwrGood = 10; /* xHCI section 5.4.9 */ 2479 for (i = 1; i <= sc->sc_noport; i++) { 2480 v = XOREAD4(sc, XHCI_PORTSC(i)); 2481 if (v & XHCI_PS_DR) 2482 hubd.DeviceRemovable[i / 8] |= 1U << (i % 8); 2483 } 2484 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2485 l = min(len, hubd.bDescLength); 2486 totlen = l; 2487 memcpy(buf, &hubd, l); 2488 break; 2489 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2490 if (len != 16) { 2491 err = USBD_IOERROR; 2492 goto ret; 2493 } 2494 memset(buf, 0, len); 2495 totlen = len; 2496 break; 2497 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2498 DPRINTFN(8,("xhci_root_ctrl_start: get port status i=%d\n", 2499 index)); 2500 if (index < 1 || index > sc->sc_noport) { 2501 err = USBD_IOERROR; 2502 goto ret; 2503 } 2504 if (len != 4) { 2505 err = USBD_IOERROR; 2506 goto ret; 2507 } 2508 v = XOREAD4(sc, XHCI_PORTSC(index)); 2509 DPRINTFN(8,("xhci_root_ctrl_start: port status=0x%04x\n", v)); 2510 i = UPS_PORT_LS_SET(XHCI_PS_GET_PLS(v)); 2511 switch (XHCI_PS_SPEED(v)) { 2512 case XHCI_SPEED_FULL: 2513 i |= UPS_FULL_SPEED; 2514 break; 2515 case XHCI_SPEED_LOW: 2516 i |= UPS_LOW_SPEED; 2517 break; 2518 case XHCI_SPEED_HIGH: 2519 i |= UPS_HIGH_SPEED; 2520 break; 2521 case XHCI_SPEED_SUPER: 2522 default: 2523 break; 2524 } 2525 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 2526 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 2527 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2528 if (v & XHCI_PS_PR) i |= UPS_RESET; 2529 if (v & XHCI_PS_PP) { 2530 if (XHCI_PS_SPEED(v) >= XHCI_SPEED_FULL && 2531 XHCI_PS_SPEED(v) <= XHCI_SPEED_HIGH) 2532 i |= UPS_PORT_POWER; 2533 else 2534 i |= UPS_PORT_POWER_SS; 2535 } 2536 USETW(ps.wPortStatus, i); 2537 i = 0; 2538 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2539 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2540 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2541 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 2542 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 2543 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 2544 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 2545 USETW(ps.wPortChange, i); 2546 l = min(len, sizeof ps); 2547 memcpy(buf, &ps, l); 2548 totlen = l; 2549 break; 2550 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2551 err = USBD_IOERROR; 2552 goto ret; 2553 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2554 break; 2555 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2556 2557 i = index >> 8; 2558 index &= 0x00ff; 2559 2560 if (index < 1 || index > sc->sc_noport) { 2561 err = USBD_IOERROR; 2562 goto ret; 2563 } 2564 port = XHCI_PORTSC(index); 2565 v = XOREAD4(sc, port) & ~XHCI_PS_CLEAR; 2566 2567 switch (value) { 2568 case UHF_PORT_ENABLE: 2569 XOWRITE4(sc, port, v | XHCI_PS_PED); 2570 break; 2571 case UHF_PORT_SUSPEND: 2572 DPRINTFN(6, ("suspend port %u (LPM=%u)\n", index, i)); 2573 if (XHCI_PS_SPEED(v) == XHCI_SPEED_SUPER) { 2574 err = USBD_IOERROR; 2575 goto ret; 2576 } 2577 XOWRITE4(sc, port, v | 2578 XHCI_PS_SET_PLS(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 2579 break; 2580 case UHF_PORT_RESET: 2581 DPRINTFN(6, ("reset port %d\n", index)); 2582 XOWRITE4(sc, port, v | XHCI_PS_PR); 2583 break; 2584 case UHF_PORT_POWER: 2585 DPRINTFN(3, ("set port power %d\n", index)); 2586 XOWRITE4(sc, port, v | XHCI_PS_PP); 2587 break; 2588 case UHF_PORT_INDICATOR: 2589 DPRINTFN(3, ("set port indicator %d\n", index)); 2590 2591 v &= ~XHCI_PS_SET_PIC(3); 2592 v |= XHCI_PS_SET_PIC(1); 2593 2594 XOWRITE4(sc, port, v); 2595 break; 2596 case UHF_C_PORT_RESET: 2597 XOWRITE4(sc, port, v | XHCI_PS_PRC); 2598 break; 2599 case UHF_C_BH_PORT_RESET: 2600 XOWRITE4(sc, port, v | XHCI_PS_WRC); 2601 break; 2602 default: 2603 err = USBD_IOERROR; 2604 goto ret; 2605 } 2606 break; 2607 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2608 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2609 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2610 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2611 break; 2612 default: 2613 err = USBD_IOERROR; 2614 goto ret; 2615 } 2616 xfer->actlen = totlen; 2617 err = USBD_NORMAL_COMPLETION; 2618 ret: 2619 xfer->status = err; 2620 s = splusb(); 2621 usb_transfer_complete(xfer); 2622 splx(s); 2623 return (err); 2624 } 2625 2626 2627 void 2628 xhci_noop(struct usbd_xfer *xfer) 2629 { 2630 } 2631 2632 2633 usbd_status 2634 xhci_root_intr_transfer(struct usbd_xfer *xfer) 2635 { 2636 usbd_status err; 2637 2638 err = usb_insert_transfer(xfer); 2639 if (err) 2640 return (err); 2641 2642 return (xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2643 } 2644 2645 usbd_status 2646 xhci_root_intr_start(struct usbd_xfer *xfer) 2647 { 2648 struct xhci_softc *sc = (struct xhci_softc *)xfer->device->bus; 2649 2650 if (sc->sc_bus.dying) 2651 return (USBD_IOERROR); 2652 2653 sc->sc_intrxfer = xfer; 2654 2655 return (USBD_IN_PROGRESS); 2656 } 2657 2658 void 2659 xhci_root_intr_abort(struct usbd_xfer *xfer) 2660 { 2661 struct xhci_softc *sc = (struct xhci_softc *)xfer->device->bus; 2662 int s; 2663 2664 sc->sc_intrxfer = NULL; 2665 2666 xfer->status = USBD_CANCELLED; 2667 s = splusb(); 2668 usb_transfer_complete(xfer); 2669 splx(s); 2670 } 2671 2672 void 2673 xhci_root_intr_done(struct usbd_xfer *xfer) 2674 { 2675 } 2676 2677 /* 2678 * Number of packets remaining in the TD after the corresponding TRB. 2679 * 2680 * Section 4.11.2.4 of xHCI specification r1.1. 2681 */ 2682 static inline uint32_t 2683 xhci_xfer_tdsize(struct usbd_xfer *xfer, uint32_t remain, uint32_t len) 2684 { 2685 uint32_t npkt, mps = UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize); 2686 2687 if (len == 0) 2688 return XHCI_TRB_TDREM(0); 2689 2690 npkt = howmany(remain - len, UE_GET_SIZE(mps)); 2691 if (npkt > 31) 2692 npkt = 31; 2693 2694 return XHCI_TRB_TDREM(npkt); 2695 } 2696 2697 /* 2698 * Transfer Burst Count (TBC) and Transfer Last Burst Packet Count (TLBPC). 2699 * 2700 * Section 4.11.2.3 of xHCI specification r1.1. 2701 */ 2702 static inline uint32_t 2703 xhci_xfer_tbc(struct usbd_xfer *xfer, uint32_t len, uint32_t *tlbpc) 2704 { 2705 uint32_t mps = UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize); 2706 uint32_t maxb, tdpc, residue, tbc; 2707 2708 /* Transfer Descriptor Packet Count, section 4.14.1. */ 2709 tdpc = howmany(len, UE_GET_SIZE(mps)); 2710 if (tdpc == 0) 2711 tdpc = 1; 2712 2713 /* Transfer Burst Count */ 2714 maxb = xhci_pipe_maxburst(xfer->pipe); 2715 tbc = howmany(tdpc, maxb + 1) - 1; 2716 2717 /* Transfer Last Burst Packet Count */ 2718 if (xfer->device->speed == USB_SPEED_SUPER) { 2719 residue = tdpc % (maxb + 1); 2720 if (residue == 0) 2721 *tlbpc = maxb; 2722 else 2723 *tlbpc = residue - 1; 2724 } else { 2725 *tlbpc = tdpc - 1; 2726 } 2727 2728 return (tbc); 2729 } 2730 2731 usbd_status 2732 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 2733 { 2734 usbd_status err; 2735 2736 err = usb_insert_transfer(xfer); 2737 if (err) 2738 return (err); 2739 2740 return (xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2741 } 2742 2743 usbd_status 2744 xhci_device_ctrl_start(struct usbd_xfer *xfer) 2745 { 2746 struct xhci_softc *sc = (struct xhci_softc *)xfer->device->bus; 2747 struct xhci_pipe *xp = (struct xhci_pipe *)xfer->pipe; 2748 struct xhci_trb *trb0, *trb; 2749 uint32_t flags, len = UGETW(xfer->request.wLength); 2750 uint8_t toggle; 2751 int s; 2752 2753 KASSERT(xfer->rqflags & URQ_REQUEST); 2754 2755 if (sc->sc_bus.dying || xp->halted) 2756 return (USBD_IOERROR); 2757 2758 if (xp->free_trbs < 3) 2759 return (USBD_NOMEM); 2760 2761 /* We'll toggle the setup TRB once we're finished with the stages. */ 2762 trb0 = xhci_xfer_get_trb(sc, xfer, &toggle, 0); 2763 2764 flags = XHCI_TRB_TYPE_SETUP | XHCI_TRB_IDT | (toggle ^ 1); 2765 if (len != 0) { 2766 if (usbd_xfer_isread(xfer)) 2767 flags |= XHCI_TRB_TRT_IN; 2768 else 2769 flags |= XHCI_TRB_TRT_OUT; 2770 } 2771 2772 memcpy(&trb0->trb_paddr, &xfer->request, sizeof(trb0->trb_paddr)); 2773 trb0->trb_status = htole32(XHCI_TRB_INTR(0) | XHCI_TRB_LEN(8)); 2774 trb0->trb_flags = htole32(flags); 2775 bus_dmamap_sync(xp->ring.dma.tag, xp->ring.dma.map, 2776 TRBOFF(&xp->ring, trb0), sizeof(struct xhci_trb), 2777 BUS_DMASYNC_PREWRITE); 2778 2779 /* Data TRB */ 2780 if (len != 0) { 2781 trb = xhci_xfer_get_trb(sc, xfer, &toggle, 0); 2782 2783 flags = XHCI_TRB_TYPE_DATA | toggle; 2784 if (usbd_xfer_isread(xfer)) 2785 flags |= XHCI_TRB_DIR_IN | XHCI_TRB_ISP; 2786 2787 trb->trb_paddr = htole64(DMAADDR(&xfer->dmabuf, 0)); 2788 trb->trb_status = htole32( 2789 XHCI_TRB_INTR(0) | XHCI_TRB_LEN(len) | 2790 xhci_xfer_tdsize(xfer, len, len) 2791 ); 2792 trb->trb_flags = htole32(flags); 2793 2794 bus_dmamap_sync(xp->ring.dma.tag, xp->ring.dma.map, 2795 TRBOFF(&xp->ring, trb), sizeof(struct xhci_trb), 2796 BUS_DMASYNC_PREWRITE); 2797 } 2798 2799 /* Status TRB */ 2800 trb = xhci_xfer_get_trb(sc, xfer, &toggle, 1); 2801 2802 flags = XHCI_TRB_TYPE_STATUS | XHCI_TRB_IOC | toggle; 2803 if (len == 0 || !usbd_xfer_isread(xfer)) 2804 flags |= XHCI_TRB_DIR_IN; 2805 2806 trb->trb_paddr = 0; 2807 trb->trb_status = htole32(XHCI_TRB_INTR(0)); 2808 trb->trb_flags = htole32(flags); 2809 2810 bus_dmamap_sync(xp->ring.dma.tag, xp->ring.dma.map, 2811 TRBOFF(&xp->ring, trb), sizeof(struct xhci_trb), 2812 BUS_DMASYNC_PREWRITE); 2813 2814 /* Setup TRB */ 2815 trb0->trb_flags ^= htole32(XHCI_TRB_CYCLE); 2816 bus_dmamap_sync(xp->ring.dma.tag, xp->ring.dma.map, 2817 TRBOFF(&xp->ring, trb0), sizeof(struct xhci_trb), 2818 BUS_DMASYNC_PREWRITE); 2819 2820 s = splusb(); 2821 XDWRITE4(sc, XHCI_DOORBELL(xp->slot), xp->dci); 2822 2823 xfer->status = USBD_IN_PROGRESS; 2824 if (xfer->timeout && !sc->sc_bus.use_polling) { 2825 timeout_del(&xfer->timeout_handle); 2826 timeout_set(&xfer->timeout_handle, xhci_timeout, xfer); 2827 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 2828 } 2829 splx(s); 2830 2831 return (USBD_IN_PROGRESS); 2832 } 2833 2834 void 2835 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 2836 { 2837 xhci_abort_xfer(xfer, USBD_CANCELLED); 2838 } 2839 2840 usbd_status 2841 xhci_device_generic_transfer(struct usbd_xfer *xfer) 2842 { 2843 usbd_status err; 2844 2845 err = usb_insert_transfer(xfer); 2846 if (err) 2847 return (err); 2848 2849 return (xhci_device_generic_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2850 } 2851 2852 usbd_status 2853 xhci_device_generic_start(struct usbd_xfer *xfer) 2854 { 2855 struct xhci_softc *sc = (struct xhci_softc *)xfer->device->bus; 2856 struct xhci_pipe *xp = (struct xhci_pipe *)xfer->pipe; 2857 struct xhci_trb *trb0, *trb; 2858 uint32_t len, remain, flags; 2859 uint32_t mps = UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize); 2860 uint64_t paddr = DMAADDR(&xfer->dmabuf, 0); 2861 uint8_t toggle; 2862 int s, i, ntrb; 2863 2864 KASSERT(!(xfer->rqflags & URQ_REQUEST)); 2865 2866 if (sc->sc_bus.dying || xp->halted) 2867 return (USBD_IOERROR); 2868 2869 /* How many TRBs do we need for this transfer? */ 2870 ntrb = howmany(xfer->length, XHCI_TRB_MAXSIZE); 2871 2872 /* If the buffer crosses a 64k boundary, we need one more. */ 2873 len = XHCI_TRB_MAXSIZE - (paddr & (XHCI_TRB_MAXSIZE - 1)); 2874 if (len < xfer->length) 2875 ntrb++; 2876 else 2877 len = xfer->length; 2878 2879 /* If we need to append a zero length packet, we need one more. */ 2880 if ((xfer->flags & USBD_FORCE_SHORT_XFER || xfer->length == 0) && 2881 (xfer->length % UE_GET_SIZE(mps) == 0)) 2882 ntrb++; 2883 2884 if (xp->free_trbs < ntrb) 2885 return (USBD_NOMEM); 2886 2887 /* We'll toggle the first TRB once we're finished with the chain. */ 2888 trb0 = xhci_xfer_get_trb(sc, xfer, &toggle, (ntrb == 1)); 2889 flags = XHCI_TRB_TYPE_NORMAL | (toggle ^ 1); 2890 if (usbd_xfer_isread(xfer)) 2891 flags |= XHCI_TRB_ISP; 2892 flags |= (ntrb == 1) ? XHCI_TRB_IOC : XHCI_TRB_CHAIN; 2893 2894 trb0->trb_paddr = htole64(DMAADDR(&xfer->dmabuf, 0)); 2895 trb0->trb_status = htole32( 2896 XHCI_TRB_INTR(0) | XHCI_TRB_LEN(len) | 2897 xhci_xfer_tdsize(xfer, xfer->length, len) 2898 ); 2899 trb0->trb_flags = htole32(flags); 2900 bus_dmamap_sync(xp->ring.dma.tag, xp->ring.dma.map, 2901 TRBOFF(&xp->ring, trb0), sizeof(struct xhci_trb), 2902 BUS_DMASYNC_PREWRITE); 2903 2904 remain = xfer->length - len; 2905 paddr += len; 2906 2907 /* Chain more TRBs if needed. */ 2908 for (i = ntrb - 1; i > 0; i--) { 2909 len = min(remain, XHCI_TRB_MAXSIZE); 2910 2911 /* Next (or Last) TRB. */ 2912 trb = xhci_xfer_get_trb(sc, xfer, &toggle, (i == 1)); 2913 flags = XHCI_TRB_TYPE_NORMAL | toggle; 2914 if (usbd_xfer_isread(xfer)) 2915 flags |= XHCI_TRB_ISP; 2916 flags |= (i == 1) ? XHCI_TRB_IOC : XHCI_TRB_CHAIN; 2917 2918 trb->trb_paddr = htole64(paddr); 2919 trb->trb_status = htole32( 2920 XHCI_TRB_INTR(0) | XHCI_TRB_LEN(len) | 2921 xhci_xfer_tdsize(xfer, remain, len) 2922 ); 2923 trb->trb_flags = htole32(flags); 2924 2925 bus_dmamap_sync(xp->ring.dma.tag, xp->ring.dma.map, 2926 TRBOFF(&xp->ring, trb), sizeof(struct xhci_trb), 2927 BUS_DMASYNC_PREWRITE); 2928 2929 remain -= len; 2930 paddr += len; 2931 } 2932 2933 /* First TRB. */ 2934 trb0->trb_flags ^= htole32(XHCI_TRB_CYCLE); 2935 bus_dmamap_sync(xp->ring.dma.tag, xp->ring.dma.map, 2936 TRBOFF(&xp->ring, trb0), sizeof(struct xhci_trb), 2937 BUS_DMASYNC_PREWRITE); 2938 2939 s = splusb(); 2940 XDWRITE4(sc, XHCI_DOORBELL(xp->slot), xp->dci); 2941 2942 xfer->status = USBD_IN_PROGRESS; 2943 if (xfer->timeout && !sc->sc_bus.use_polling) { 2944 timeout_del(&xfer->timeout_handle); 2945 timeout_set(&xfer->timeout_handle, xhci_timeout, xfer); 2946 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 2947 } 2948 splx(s); 2949 2950 return (USBD_IN_PROGRESS); 2951 } 2952 2953 void 2954 xhci_device_generic_done(struct usbd_xfer *xfer) 2955 { 2956 /* Only happens with interrupt transfers. */ 2957 if (xfer->pipe->repeat) { 2958 xfer->actlen = 0; 2959 xhci_device_generic_start(xfer); 2960 } 2961 } 2962 2963 void 2964 xhci_device_generic_abort(struct usbd_xfer *xfer) 2965 { 2966 KASSERT(!xfer->pipe->repeat || xfer->pipe->intrxfer == xfer); 2967 2968 xhci_abort_xfer(xfer, USBD_CANCELLED); 2969 } 2970 2971 usbd_status 2972 xhci_device_isoc_transfer(struct usbd_xfer *xfer) 2973 { 2974 usbd_status err; 2975 2976 err = usb_insert_transfer(xfer); 2977 if (err && err != USBD_IN_PROGRESS) 2978 return (err); 2979 2980 return (xhci_device_isoc_start(xfer)); 2981 } 2982 2983 usbd_status 2984 xhci_device_isoc_start(struct usbd_xfer *xfer) 2985 { 2986 struct xhci_softc *sc = (struct xhci_softc *)xfer->device->bus; 2987 struct xhci_pipe *xp = (struct xhci_pipe *)xfer->pipe; 2988 struct xhci_xfer *xx = (struct xhci_xfer *)xfer; 2989 struct xhci_trb *trb0, *trb; 2990 uint32_t len, remain, flags; 2991 uint64_t paddr; 2992 uint32_t tbc, tlbpc; 2993 int s, i, j, ntrb = xfer->nframes; 2994 uint8_t toggle; 2995 2996 KASSERT(!(xfer->rqflags & URQ_REQUEST)); 2997 2998 if (sc->sc_bus.dying || xp->halted) 2999 return (USBD_IOERROR); 3000 3001 /* Why would you do that anyway? */ 3002 if (sc->sc_bus.use_polling) 3003 return (USBD_INVAL); 3004 3005 /* 3006 * To allow continuous transfers, above we start all transfers 3007 * immediately. However, we're still going to get usbd_start_next call 3008 * this when another xfer completes. So, check if this is already 3009 * in progress or not 3010 */ 3011 if (xx->ntrb > 0) 3012 return (USBD_IN_PROGRESS); 3013 3014 paddr = DMAADDR(&xfer->dmabuf, 0); 3015 3016 /* How many TRBs do for all Transfers? */ 3017 for (i = 0, ntrb = 0; i < xfer->nframes; i++) { 3018 /* How many TRBs do we need for this transfer? */ 3019 ntrb += howmany(xfer->frlengths[i], XHCI_TRB_MAXSIZE); 3020 3021 /* If the buffer crosses a 64k boundary, we need one more. */ 3022 len = XHCI_TRB_MAXSIZE - (paddr & (XHCI_TRB_MAXSIZE - 1)); 3023 if (len < xfer->frlengths[i]) 3024 ntrb++; 3025 3026 paddr += xfer->frlengths[i]; 3027 } 3028 3029 if (xp->free_trbs < ntrb) 3030 return (USBD_NOMEM); 3031 3032 paddr = DMAADDR(&xfer->dmabuf, 0); 3033 3034 for (i = 0, trb0 = NULL; i < xfer->nframes; i++) { 3035 /* How many TRBs do we need for this transfer? */ 3036 ntrb = howmany(xfer->frlengths[i], XHCI_TRB_MAXSIZE); 3037 3038 /* If the buffer crosses a 64k boundary, we need one more. */ 3039 len = XHCI_TRB_MAXSIZE - (paddr & (XHCI_TRB_MAXSIZE - 1)); 3040 if (len < xfer->frlengths[i]) 3041 ntrb++; 3042 else 3043 len = xfer->frlengths[i]; 3044 3045 KASSERT(ntrb < 3); 3046 3047 /* 3048 * We'll commit the first TRB once we're finished with the 3049 * chain. 3050 */ 3051 trb = xhci_xfer_get_trb(sc, xfer, &toggle, (ntrb == 1)); 3052 3053 DPRINTFN(4, ("%s:%d: ring %p trb0_idx %lu ntrb %d paddr %llx " 3054 "len %u\n", __func__, __LINE__, 3055 &xp->ring.trbs[0], (trb - &xp->ring.trbs[0]), ntrb, paddr, 3056 len)); 3057 3058 /* Record the first TRB so we can toggle later. */ 3059 if (trb0 == NULL) { 3060 trb0 = trb; 3061 toggle ^= 1; 3062 } 3063 3064 flags = XHCI_TRB_TYPE_ISOCH | XHCI_TRB_SIA | toggle; 3065 if (usbd_xfer_isread(xfer)) 3066 flags |= XHCI_TRB_ISP; 3067 flags |= (ntrb == 1) ? XHCI_TRB_IOC : XHCI_TRB_CHAIN; 3068 3069 tbc = xhci_xfer_tbc(xfer, xfer->frlengths[i], &tlbpc); 3070 flags |= XHCI_TRB_ISOC_TBC(tbc) | XHCI_TRB_ISOC_TLBPC(tlbpc); 3071 3072 trb->trb_paddr = htole64(paddr); 3073 trb->trb_status = htole32( 3074 XHCI_TRB_INTR(0) | XHCI_TRB_LEN(len) | 3075 xhci_xfer_tdsize(xfer, xfer->frlengths[i], len) 3076 ); 3077 trb->trb_flags = htole32(flags); 3078 3079 bus_dmamap_sync(xp->ring.dma.tag, xp->ring.dma.map, 3080 TRBOFF(&xp->ring, trb), sizeof(struct xhci_trb), 3081 BUS_DMASYNC_PREWRITE); 3082 3083 remain = xfer->frlengths[i] - len; 3084 paddr += len; 3085 3086 /* Chain more TRBs if needed. */ 3087 for (j = ntrb - 1; j > 0; j--) { 3088 len = min(remain, XHCI_TRB_MAXSIZE); 3089 3090 /* Next (or Last) TRB. */ 3091 trb = xhci_xfer_get_trb(sc, xfer, &toggle, (j == 1)); 3092 flags = XHCI_TRB_TYPE_NORMAL | toggle; 3093 if (usbd_xfer_isread(xfer)) 3094 flags |= XHCI_TRB_ISP; 3095 flags |= (j == 1) ? XHCI_TRB_IOC : XHCI_TRB_CHAIN; 3096 DPRINTFN(3, ("%s:%d: ring %p trb0_idx %lu ntrb %d " 3097 "paddr %llx len %u\n", __func__, __LINE__, 3098 &xp->ring.trbs[0], (trb - &xp->ring.trbs[0]), ntrb, 3099 paddr, len)); 3100 3101 trb->trb_paddr = htole64(paddr); 3102 trb->trb_status = htole32( 3103 XHCI_TRB_INTR(0) | XHCI_TRB_LEN(len) | 3104 xhci_xfer_tdsize(xfer, remain, len) 3105 ); 3106 trb->trb_flags = htole32(flags); 3107 3108 bus_dmamap_sync(xp->ring.dma.tag, xp->ring.dma.map, 3109 TRBOFF(&xp->ring, trb), sizeof(struct xhci_trb), 3110 BUS_DMASYNC_PREWRITE); 3111 3112 remain -= len; 3113 paddr += len; 3114 } 3115 3116 xfer->frlengths[i] = 0; 3117 } 3118 3119 /* First TRB. */ 3120 trb0->trb_flags ^= htole32(XHCI_TRB_CYCLE); 3121 bus_dmamap_sync(xp->ring.dma.tag, xp->ring.dma.map, 3122 TRBOFF(&xp->ring, trb0), sizeof(struct xhci_trb), 3123 BUS_DMASYNC_PREWRITE); 3124 3125 s = splusb(); 3126 XDWRITE4(sc, XHCI_DOORBELL(xp->slot), xp->dci); 3127 3128 xfer->status = USBD_IN_PROGRESS; 3129 3130 if (xfer->timeout) { 3131 timeout_del(&xfer->timeout_handle); 3132 timeout_set(&xfer->timeout_handle, xhci_timeout, xfer); 3133 timeout_add_msec(&xfer->timeout_handle, xfer->timeout); 3134 } 3135 splx(s); 3136 3137 return (USBD_IN_PROGRESS); 3138 } 3139