Implement support for deeper idle states offered by PSCI. Reduces the
idle power usage of the Vivobook S15 by almost 50%.

ok patrick@

Renove unused function and prototype.

ok jsg@

Implement Spectre-V4 mitigations. The only real effect of this change is
that we now make a firmware call to enable the mitigations if the
firmware tells us mitigations are implemented and needed.

Implement Spectre-V4 mitigations. The only real effect of this change is
that we now make a firmware call to enable the mitigations if the
firmware tells us mitigations are implemented and needed. But according
to the specification these mitigations should be enabled by default.
The open source TF-A implementation only implements mitigations for older
Cortex-A76 cores. Newer Cortex-A76 revisions are not vulnerable and as
far as I can tell we only support SoCs with the newer cores.

ok patrick@

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Add support for deep(er) idle states that can be entered using PSCI. For
now this only supports states advertised in device trees, but ACPI support
could be added as well. The parsing of the idle s

Add support for deep(er) idle states that can be entered using PSCI. For
now this only supports states advertised in device trees, but ACPI support
could be added as well. The parsing of the idle states as well as the
heuristic to pick the deepest one is probably a bit to simple, but more
complex cases can be added later. Worst case cores will use WFI and use
more power in suspend.

ok phessler@

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Add a driver for the ARM System Control and Management Interface, which,
among other things allows management of clocks under firmware management.

ok patrick@

Mitigate Spectre-BHB by using core-specific trampoline vectors. On some cores
Spectre-BHB can be mitigated by using a loop that branches a number of times.
For cores where this does not suffice, or

Mitigate Spectre-BHB by using core-specific trampoline vectors. On some cores
Spectre-BHB can be mitigated by using a loop that branches a number of times.
For cores where this does not suffice, or where Spectre-V2 needs to be handled
as well, try and call into a new PSCI function that mitigates both Spectre-V2
and Spectre-BHB. Some newer machines, which might not be in anyone's hands
yet, have an instruction (CLRBHB) that clears the BHB. If ECBHB is set, the
BHB isn't vulnerable. If we have CSV2_3/HCXT, it's not vulnerable at all.

No visible performance dropoff on a MacchiatoBin (4xA72) or Lenovo x13s (4xA78C+
4xX1C), but around 2-3% on a LX2K (16xA72) and RK3399 (4xA53+2xA72).

ok kettenis@

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Add support for calling the CPU_OFF and SYSTEM_SUSPEND functions.
Add a function to check whether SYSTEM_SUSPEND is supported by the
PSCI firmware.

ok patrick@

Constify struct cfattach.

ok visa@ a long time ago, ok patrick@

Apparently it is possible for firmware to indicate that SMCCC_VERSION is
implemented but have that call return NOT_SUPPORTED. Makes no sense,
but the SMCCC standard documents this and tells us to tr

Apparently it is possible for firmware to indicate that SMCCC_VERSION is
implemented but have that call return NOT_SUPPORTED. Makes no sense,
but the SMCCC standard documents this and tells us to treat this as v1.0.
Change the code accordingly. Turn a few checks that should always be true
into KASSERTs to keep the control flow simple.

ok patrick@

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Simplify the CVE-2017-5715 workaround code. Marvell backported SMSCCC 1.1
support to their ATF fork and I expect other vendors that bothered to
backport the early workaround to do the same. And ano

Simplify the CVE-2017-5715 workaround code. Marvell backported SMSCCC 1.1
support to their ATF fork and I expect other vendors that bothered to
backport the early workaround to do the same. And another ATF update is
needed anyway to implement the workaround for Spectre variant 4i
(CVE-2018-3639).

ok patrick@, mlarkin@, jsg@

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Add support for SMCCC 1.1 which provides proper support for the firmware-based
workaround for branch target injection attacks (CVE 2017-5715).

ok patrick@, jsg@

Get rid of the cpu_on_fn hook and call the psci(4) functions directly instead
like we already do in the code that flushes the BTB.

ok jsg@

Store PSCI function ids as uint32_t not int in the softc.
Avoids unwanted sign extension on arm64 that resulted in qemu not
recognising the function ids and matches the specification.

Problem report

Store PSCI function ids as uint32_t not int in the softc.
Avoids unwanted sign extension on arm64 that resulted in qemu not
recognising the function ids and matches the specification.

Problem reported by semarie@
ok kettenis@

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Implement support for the PSCI_VERSION call and export the function such that
we can use it to defend against branch target injection attacks.

ok patrick@, visa@

Use register_t instead of uint32_t in smc/hmc calls such that arguments
to SMC64 functions don't get truncated. Implement support for the CPU_ON
call.

Add support for the older generation spec of PSCI, which supports
shutdown and reset only if the function id is explicitly provided
in the device tree. For the newer implementations we are supposed

Add support for the older generation spec of PSCI, which supports
shutdown and reset only if the function id is explicitly provided
in the device tree. For the newer implementations we are supposed
to be using the specified function ids only.

With and ok jsg@

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Move psci(4) and plrtc(4) so arm64 can use them.
Tested by and ok patrick@