Make it clearer where message "spurious interrupt" comes from.

Let each interrupt controller driver choose how to implement
intr_barrier(9).

With this change, the barrier should finally work properly with
cnmac(4) interrupts that have been assigned to secondary

Let each interrupt controller driver choose how to implement
intr_barrier(9).

With this change, the barrier should finally work properly with
cnmac(4) interrupts that have been assigned to secondary cores.

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Include header <sys/evcount.h> where event counters are used, so that
header <machine/intr.h> can eventually stop including it on octeon.

Assume edge triggering by default for robustness, as is done
in octcit(4).

Add a driver for the CIB interrupt controller. Certain device
controllers need it on CN70xx/CN71xx.