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130ea1ec |
| 18-Aug-2024 |
deraadt <deraadt@openbsd.org> |
don't need to put config_activate_children inside cfattach, because NULL means the same ok kettenis
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e3ee5e84 |
| 12-Mar-2022 |
mpi <mpi@openbsd.org> |
Constify struct cfattach.
ok patrick@
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37084e1e |
| 29-Apr-2020 |
kettenis <kettenis@openbsd.org> |
Let the armv7 bus_dma layer and simplebus(4) implementation deal with DMA remapping in the same way as arm64. This relies on the dma-ranges property in the device tree and allows us to get rid of th
Let the armv7 bus_dma layer and simplebus(4) implementation deal with DMA remapping in the same way as arm64. This relies on the dma-ranges property in the device tree and allows us to get rid of the hack for the Raspberry Pi in the dwctwo(4) driver.
Note that this does not include the hack in simplebus(4) that we have on arm64 since firmware that has the dma-ranges is in widespread use now.
ok patrick@
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79645871 |
| 02-May-2016 |
patrick <patrick@openbsd.org> |
Rework mainbus and implement simplebus to be able to span a tree-like topology based on device tree information. Introduce a common attach args structure to be used for all fdt-capable bus devices.
Rework mainbus and implement simplebus to be able to span a tree-like topology based on device tree information. Introduce a common attach args structure to be used for all fdt-capable bus devices.
ok jsg@ kettenis@
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72d97272 |
| 08-Apr-2016 |
patrick <patrick@openbsd.org> |
Fix match function so that the cortex bus only attaches if the attach args are actually looking for the cortex bus.
ok kettenis@
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4ccb6786 |
| 29-May-2015 |
jsg <jsg@openbsd.org> |
add some more cortex A ids
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8ff1d18e |
| 06-Aug-2013 |
patrick <patrick@openbsd.org> |
The Cortex bus should be useful for Cortex-A7, too.
ok rapha@ jsg@
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027018ef |
| 01-May-2013 |
patrick <patrick@openbsd.org> |
Add a cortex bus which represents the ARM MPCore Complex. It will attach only to ARM Cortex A9 and A15 SoCs. The generic interrupt controller and timer will attach to this bus, later a secondary cach
Add a cortex bus which represents the ARM MPCore Complex. It will attach only to ARM Cortex A9 and A15 SoCs. The generic interrupt controller and timer will attach to this bus, later a secondary cache controller can be added. The base address for those controllers are figured out using the periphbase register.
ok bmercer@
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