Minor style fixes to asm codes. No binary changes.

copy{in,out}str: As a tiny optimization, drop redundant mtpid.

No regression for ATF on 405. 403 seems to work fine.

copy{in,out}str: Consistently use tmp as scratch register. NFC.

copy{in,out}str: "insn[TAB]operands;" for inline asm codes.

copy{in,out}str: Style sync with copy{in,out}. No binary changes.

copy{in,out}{,str}: Drop needless dcbst.

Data cache is purely physical for 40[53] with 16KB pages, and therefore
no need to flush cache before context switch.

This significantly improves copy{in,ou

copy{in,out}{,str}: Drop needless dcbst.

Data cache is purely physical for 40[53] with 16KB pages, and therefore
no need to flush cache before context switch.

This significantly improves copy{in,out} against small data; for example,
bytebench on DHT becomes:

-Pipe Throughput 12440.0 8826.1 7.1
+Pipe Throughput 12440.0 18364.8 14.8

No performance/ATF regression observed on 405. 403 boots successfully
into multiuser mode, and builds some packages.

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copy{in,out}str: Add cr0 and ctr to list of clobbered registers.

copy{in,out}str: Consistently use uaddr instead of udaddr.
Note that we use kaddr, not kdaddr, for kernel data address.

copy{in,out}str: Tidy up inline asm's:
- Use %[foo], %[bar], ... instead of %0, %1, ...
- One instruction per line.
- Paragraph grouped instructions.
- Fix wrong comments.
No binary changes.

Make ibm4xx kernels compiled by clang.

As clang cannot correctly assemble m[ft]pid:
- for asm sources, use m[ft]spr from/to SPR_PID
- for C sources, use M[FT]PID macros (see include/ibm4xx/spr.h)
Th

Make ibm4xx kernels compiled by clang.

As clang cannot correctly assemble m[ft]pid:
- for asm sources, use m[ft]spr from/to SPR_PID
- for C sources, use M[FT]PID macros (see include/ibm4xx/spr.h)
This is ugly...

No binary changes for GCC-compiled kernels.

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Try to sanitize usage of isync and sync instructions.

According to reference manuals of 4xx, isync is "context synchronization",
which satisfies both 1 and 2:

1. instructions preceding it complete

Try to sanitize usage of isync and sync instructions.

According to reference manuals of 4xx, isync is "context synchronization",
which satisfies both 1 and 2:

1. instructions preceding it complete in the context that existed before it
2. instructions following it complete in the context that exists after it

Whereas sync (== msync for 440) is "execution synchronization", which
satisfies just 1, not 2. At the same time, sync guarantees "storage
synchronization", by which any previous storage references completes
before any subsequent instructions begin to execute.

Tested on 405 over months.

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Cosmetic changes. No binary changes.

Use dcbst instead of dcbf to flush cache; the former does not invalidate
the cache line, which should be used immediately in most cases.

copy{in,out}str: Correctly return ENAMETOOLONG if source is not
NUL-terminated.

copy{in,out}str: sync style with booke.

- early return in case of len == 0
- *done = 0 on fault

fix copy{in,out}{,str}() to return the error returned by uvm_fault().
fixes PR 41813.

bare asm -> __asm

merge ktrace-lwp.

Apply suggested changes from PR port-powerpc/24830 arch/powerpc/ibm4xx:
Bad register constraints in copyin(), copyout(), copyinstr(), copyoutstr(),
and delay().

Remove some numeric asm labels that aren't used.

__KERNEL_RCSID()

Perform a rototill of the powerpc code. Mandate use of SPRG0 to store
a pointer to current cpu's cpu_info structure. Use cpu_info for
intstk,intr_depth,still_stk,idle_pcb,curpcb,curlwp,etal even on

Perform a rototill of the powerpc code. Mandate use of SPRG0 to store
a pointer to current cpu's cpu_info structure. Use cpu_info for
intstk,intr_depth,still_stk,idle_pcb,curpcb,curlwp,etal even on
non-MULTIPROCESSOR machines. Add common macros GET_CPUINFO and
INIT_CPUINFO to get and initialize the cpu_info struct on startup. Make
ibm4xx use the standard <powerpc/frame.h>. Use IFRAME_xx in ibm4xx
trap_subr.S instead of explicit magic offsets. Move INTSTK and SPILLSTK
to std.<platform>. Change faultbuf to a struct instead of an array.

On MPC6XX cpus, stop using the vector page for temporary space and use
reserved space in cpu_info.

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Clean up some white space niggles.

Add a port to IBM's PPC405GP Reference Board (the "walnut")
by Eduardo Horvath and Simon Burge of Wasabi Systems.

IBM 4xx series CPU features:
- New pmap and revised trap handler.
- Support on-chi

Add a port to IBM's PPC405GP Reference Board (the "walnut")
by Eduardo Horvath and Simon Burge of Wasabi Systems.

IBM 4xx series CPU features:
- New pmap and revised trap handler.
- Support on-chip timers, PCI controller, UARTs
- Framework for on-chip ethernet and watchdog timer.
General PowerPC features:
- Add in-kernel PPC floating point emulation
- New in{,4}_cksum that is between 1.5 and 5 times faster than the
old version depending on CPU type.
General changes:
- Kernel support for generic dbsym-style symbols.

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