fix various typos, mainly in comments.

Welcome XENPVHVM mode.

It is UP only, has xbd(4) and xennet(4) as PV drivers.

The console is com0 at isa and the native portion is very
rudimentary AT architecture, so is probably suboptimal to
run

Welcome XENPVHVM mode.

It is UP only, has xbd(4) and xennet(4) as PV drivers.

The console is com0 at isa and the native portion is very
rudimentary AT architecture, so is probably suboptimal to
run without PV support.

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We reorganise definitions for XEN source support as follows:

XEN - common sources required for baseline XEN support.
XENPV - sources required for support of XEN in PV mode.
XENPVHVM - sources requir

We reorganise definitions for XEN source support as follows:

XEN - common sources required for baseline XEN support.
XENPV - sources required for support of XEN in PV mode.
XENPVHVM - sources required for support for XEN in HVM mode.
XENPVH - sources required for support for XEN in PVH mode.

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Hide differences between i386 and amd64 interrupt frames so XEN does
not need to know there is one. Hopefully unbreak i386 build.

Remove the vm86 fields from the trap frame. It seems to me that we could
now remove the '-16' when initializing pcb_esp0.

add an lwp_trapframe() interface to return an LWP's user trapframe.
needed by dtrace.

Remove COMPAT_SA / KERN_SA. Welcome to 6.99.3!
Approved by core@.

Replace the trapframe fields for segment registers with two uint16_t
fields - one of which is an explicit pad.

Wrap sigframe_sigcontext in _KERNEL

Remove some compat ifdefs that aren't really needed.

Merge wrstuden-revivesa into HEAD.

Remove clause 3 and 4 from TNF licenses

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the v

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

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merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.

merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

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Merge newlock2 to head.

u_intN_t -> uintN_t

constify sendsig/trapsignal

expose sendsig_sigcontext for compat_16

#ifdef struct sigframe_sigcontext and struct sigcontext, so that only code
that really needs them, get them.
XXX1: We need to fix the vm86 api.
XXX2: We need to fix the ibcs2 signal delivery mechanis

#ifdef struct sigframe_sigcontext and struct sigcontext, so that only code
that really needs them, get them.
XXX1: We need to fix the vm86 api.
XXX2: We need to fix the ibcs2 signal delivery mechanism.

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SA_SIGINFO changes.

Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.

Merge the nathanw_sa branch.

New interrupt code. The basic idea behind it is to hide the differences
in interrupt controllers in struct pic, and try to keep as much
common code as possible. At the lowest (asm) level, this is don

New interrupt code. The basic idea behind it is to hide the differences
in interrupt controllers in struct pic, and try to keep as much
common code as possible. At the lowest (asm) level, this is done
with CPP macros.

The main structure is now struct intrsource, describing an established
interrupt line, of any kind (soft/hard local apic/legacy apic/IO apic).
For quick masking, there may be a maximum of 32 sources per CPU.
Sources can be assigned to any CPU in the MP case, though currently they
all go to the boot CPU.

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Merge Bill Sommerfeld's i386 MP branch. This code has some known
caveats, but works quite well in a lot of MP cases, and all
UP cases that I have tested. Parts of this will hopefully be
reworked in t

Merge Bill Sommerfeld's i386 MP branch. This code has some known
caveats, but works quite well in a lot of MP cases, and all
UP cases that I have tested. Parts of this will hopefully be
reworked in the not-too-distant future.

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During native signal delivery (and iBCS2, since it uses the native
sigcode), arrange to have the signal handler invoked directly, using
the trampoline only for the return path, saving a call insn. P

During native signal delivery (and iBCS2, since it uses the native
sigcode), arrange to have the signal handler invoked directly, using
the trampoline only for the return path, saving a call insn. Play
some other stack trickery in the trampoline to turn 2 pushl's into
one movl.

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