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Revision tags: llvmorg-21-init |
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4e8c9d28 |
| 16-Jan-2025 |
Jay Foad <jay.foad@amd.com> |
[TableGen] Use std::pair instead of std::make_pair. NFC. (#123174)
Also use brace initialization and emplace to avoid explicitly
constructing std::pair, and the same for std::tuple.
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Revision tags: llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0 |
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| #
7c6592f5 |
| 11-Sep-2024 |
Rahul Joshi <rjoshi@nvidia.com> |
[TableGen] Change CodeGenRegister to use const Record pointer (#108027)
Change CodeGenRegister to use const Record pointer.
This is a part of effort to have better const correctness in TableGen
[TableGen] Change CodeGenRegister to use const Record pointer (#108027)
Change CodeGenRegister to use const Record pointer.
This is a part of effort to have better const correctness in TableGen
backends:
https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
show more ...
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| #
985600dc |
| 09-Sep-2024 |
Rahul Joshi <rjoshi@nvidia.com> |
[TableGen] Migrate CodeGenHWModes to use const RecordKeeper (#107851)
Migrate CodeGenHWModes to use const RecordKeeper and const Record
pointers.
This is a part of effort to have better const co
[TableGen] Migrate CodeGenHWModes to use const RecordKeeper (#107851)
Migrate CodeGenHWModes to use const RecordKeeper and const Record
pointers.
This is a part of effort to have better const correctness in TableGen
backends:
https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
show more ...
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Revision tags: llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3 |
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| #
baf66ec0 |
| 27-Mar-2024 |
Craig Topper <craig.topper@sifive.com> |
[Target][RISCV] Add HwMode support to subregister index size/offset. (#86368)
This is needed to provide proper size and offset for the GPRPair subreg
indices on RISC-V. The size of a GPR already us
[Target][RISCV] Add HwMode support to subregister index size/offset. (#86368)
This is needed to provide proper size and offset for the GPRPair subreg
indices on RISC-V. The size of a GPR already uses HwMode. Previously we
said the subreg indices have unknown size and offset, but this stops
DwarfExpression::addMachineReg from being able to find the registers
that make up the pair.
I believe this fixes https://github.com/llvm/llvm-project/issues/85864
but need to verify.
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fa3d789d |
| 25-Mar-2024 |
Pierre van Houtryve <pierre.vanhoutryve@amd.com> |
[RFC][TableGen] Restructure TableGen Source (#80847)
Refactor of the llvm-tblgen source into:
- a "Basic" library, which contains the bare minimum utilities to build
`llvm-min-tablegen`
- a "Comm
[RFC][TableGen] Restructure TableGen Source (#80847)
Refactor of the llvm-tblgen source into:
- a "Basic" library, which contains the bare minimum utilities to build
`llvm-min-tablegen`
- a "Common" library which contains all of the helpers for TableGen
backends. Such helpers can be shared by more than one backend, and even
unit tested (e.g. CodeExpander is, maybe we can add more over time)
Fixes #80647
show more ...
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