[TableGen] Use std::pair instead of std::make_pair. NFC. (#123174)

Also use brace initialization and emplace to avoid explicitly
constructing std::pair, and the same for std::tuple.

[TableGen] Fix calculation of Lanemask for RCs with artificial subregs. (#114392)

TableGen builds up a map of "SubRegIdx -> Subclass" where Subclass is
the largest class where all registers have Su

[TableGen] Fix calculation of Lanemask for RCs with artificial subregs. (#114392)

TableGen builds up a map of "SubRegIdx -> Subclass" where Subclass is
the largest class where all registers have SubRegIdx as a sub-register.
When SubRegIdx (vis-a-vis the sub-register) is artificial it should
still include it in the map. This map is used in various places,
including in the calculation of the Lanemask of a register class, which
otherwise calculates an incorrect lanemask.

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[TableGen] Fix concatenation of subreg and artificial subregs (#114391)

When CoveredBySubRegs is true and a sub-register consists of two
parts; a regular subreg and an artificial subreg, then Table

[TableGen] Fix concatenation of subreg and artificial subregs (#114391)

When CoveredBySubRegs is true and a sub-register consists of two
parts; a regular subreg and an artificial subreg, then TableGen
should consider only concatenating the non-artificial subregs.
For example, S0_S1 is a concatenated subreg from D0_D1,
but S0_S1_HI should not be considered.

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[NFC][LLVM][TableGen] Change `RecordKeeper::getClass` to return const pointer (#112261)

Change `RecordKeeper::getClass` to return const record pointer. This is
a part of effort to have better const

[NFC][LLVM][TableGen] Change `RecordKeeper::getClass` to return const pointer (#112261)

Change `RecordKeeper::getClass` to return const record pointer. This is
a part of effort to have better const correctness in TableGen backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089

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[LLVM][TableGen] Change all `Init` pointers to const (#112705)

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-

[LLVM][TableGen] Change all `Init` pointers to const (#112705)

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089

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[NFC][TableGen] Change `Record::getSuperClasses` to use const Record* (#110845)

Change `Record::getSuperClasses` to return a const pointer to the
superclass records.

This is a part of effort to

[NFC][TableGen] Change `Record::getSuperClasses` to use const Record* (#110845)

Change `Record::getSuperClasses` to return a const pointer to the
superclass records.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089

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[TableGen] Change `getValueAsListOfDefs` to return const pointer vector (#110713)

Change `getValueAsListOfDefs` to return a vector of const Record
pointer, and remove `getValueAsListOfConstDefs` th

[TableGen] Change `getValueAsListOfDefs` to return const pointer vector (#110713)

Change `getValueAsListOfDefs` to return a vector of const Record
pointer, and remove `getValueAsListOfConstDefs` that was added as a
transition aid.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089

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[TableGen] Change all type pointers to const (#110602)

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-table

[TableGen] Change all type pointers to const (#110602)

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089

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[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467)

Use const record pointers in TableGen/Common files.

This is a part of effort to have better const correctness in Tabl

[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467)

Use const record pointers in TableGen/Common files.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089

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[TableGen] Change CodeGenRegister to use const Record pointer (#108027)

Change CodeGenRegister to use const Record pointer.

This is a part of effort to have better const correctness in TableGen

[TableGen] Change CodeGenRegister to use const Record pointer (#108027)

Change CodeGenRegister to use const Record pointer.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089

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[TableGen] Change CGIOperandList::OperandInfo::Rec to const pointer (#107858)

Change CGIOperandList::OperandInfo::Rec and CGIOperandList::TheDef to
const pointer.

This is a part of effort to hav

[TableGen] Change CGIOperandList::OperandInfo::Rec to const pointer (#107858)

Change CGIOperandList::OperandInfo::Rec and CGIOperandList::TheDef to
const pointer.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089

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[TableGen] Change SetTheory set/vec to use const Record * (#107692)

Change SetTheory::RecSet/RecVec to use const Record pointers.

[NFC][TableGen] Replace DefInit::get() with Record::getDefInit() (#107762)

Eliminate DefInit::get() as its a duplicate of Record::getDefInit().
Use early return in `VarDefInit::instantiate`.

[NFC][SetTheory] Refactor to use const pointers and range loops (#105544)

- Refactor SetTheory code to use const pointers when possible.
- Use auto for variables initialized using dyn_cast<>.
- Us

[NFC][SetTheory] Refactor to use const pointers and range loops (#105544)

- Refactor SetTheory code to use const pointers when possible.
- Use auto for variables initialized using dyn_cast<>.
- Use range based for loops and early continue.

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[TableGen] Check for duplicate register tuple definitions. (#95725)

Currently TableGen does not directly detect duplicate synthesized
registers as can happen in this example:

def GPR128 : Regist

[TableGen] Check for duplicate register tuple definitions. (#95725)

Currently TableGen does not directly detect duplicate synthesized
registers as can happen in this example:

def GPR128 : RegisterTuples<[sub0, sub1, sub2, sub3],
[(decimate (shl GPR32, 0), 1),
(decimate (shl GPR32, 1), 1),
(decimate (shl GPR32, 2), 1),
(decimate (shl GPR32, 3), 1)]>;

def GPR128_Aligned : RegisterTuples<[sub0, sub1, sub2, sub3],
[(decimate (shl GPR32, 0), 4),
(decimate (shl GPR32, 1), 4),
(decimate (shl GPR32, 2), 4),
(decimate (shl GPR32, 3), 4)]>;

TableGen does fail, but with an unrelated and difficult to understand
error that happens downstream of tuple expansion:
"error: No SubRegIndex for R0_R1_R2_R3 in R0_R1_R2_R3".

This patch detects the problem directly during expansion and emits an
error pointing the user to the actual issue:
"error: Register tuple redefines register 'R0_R1_R2_R3'".

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[TableGen] Use llvm::unique (NFC) (#94163)

[Target][RISCV] Add HwMode support to subregister index size/offset. (#86368)

This is needed to provide proper size and offset for the GPRPair subreg
indices on RISC-V. The size of a GPR already us

[Target][RISCV] Add HwMode support to subregister index size/offset. (#86368)

This is needed to provide proper size and offset for the GPRPair subreg
indices on RISC-V. The size of a GPR already uses HwMode. Previously we
said the subreg indices have unknown size and offset, but this stops
DwarfExpression::addMachineReg from being able to find the registers
that make up the pair.

I believe this fixes https://github.com/llvm/llvm-project/issues/85864
but need to verify.

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[RFC][TableGen] Restructure TableGen Source (#80847)

Refactor of the llvm-tblgen source into:
- a "Basic" library, which contains the bare minimum utilities to build
`llvm-min-tablegen`
- a "Comm

[RFC][TableGen] Restructure TableGen Source (#80847)

Refactor of the llvm-tblgen source into:
- a "Basic" library, which contains the bare minimum utilities to build
`llvm-min-tablegen`
- a "Common" library which contains all of the helpers for TableGen
backends. Such helpers can be shared by more than one backend, and even
unit tested (e.g. CodeExpander is, maybe we can add more over time)

Fixes #80647

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