#
ed6ddffb |
| 25-Oct-2024 |
dong-miao <601183878@qq.com> |
[RISCV] Add Smrnmi extension (#111668)
This commit has completed the Extension for Resumable Non Maskable
Interrupts, adding four CRSs and one Trap-Return instruction.
Specification link:["Smrnmi"
[RISCV] Add Smrnmi extension (#111668)
This commit has completed the Extension for Resumable Non Maskable
Interrupts, adding four CRSs and one Trap-Return instruction.
Specification link:["Smrnmi"
Extension](https://github.com/riscv/riscv-isa-manual/blob/main/src/rnmi.adoc)
---------
Co-authored-by: Sam Elliott <sam@lenary.co.uk>
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Revision tags: llvmorg-19.1.2, llvmorg-19.1.1 |
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#
614aeda9 |
| 25-Sep-2024 |
Alex Bradbury <asb@igalia.com> |
[RISCV] Mark Zacas as non-experimental (#109651)
The extension has been ratified for some time, but we kept it
experimental (see #99898) due to
<https://github.com/riscv-non-isa/riscv-elf-psabi-do
[RISCV] Mark Zacas as non-experimental (#109651)
The extension has been ratified for some time, but we kept it
experimental (see #99898) due to
<https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/444>. The
ABI issue has been resolved by #101023 so I believe there's no known
barrier to moving Zacas to non-experimental.
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Revision tags: llvmorg-19.1.0, llvmorg-19.1.0-rc4 |
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#
0ca77f66 |
| 22-Aug-2024 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Add CSRs and an instruction for Smctr and Ssctr extensions. (#105148)
https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc3
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#
bacedb56 |
| 21-Aug-2024 |
Shao-Ce SUN <sunshaoce@outlook.com> |
[RISCV] Remove experimental for Ssqosid ext (#105476)
Ratified: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0
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Revision tags: llvmorg-19.1.0-rc3 |
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#
371f936c |
| 17-Aug-2024 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Make extension names lower case in RISCVISAInfo::checkDependency() error messages.
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#
d489b7cc |
| 16-Aug-2024 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Merge some ISA error reporting together and make some errors more precise.
Loop over the extension names that have the same error message.
Print the name of Zvk* extensions instead of 'zvk*
[RISCV] Merge some ISA error reporting together and make some errors more precise.
Loop over the extension names that have the same error message.
Print the name of Zvk* extensions instead of 'zvk*'.
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#
f802c39c |
| 17-Aug-2024 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Add more tests for RISCVISAInfo::checkDependency(). NFC
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#
a80a90e3 |
| 19-Aug-2024 |
Pengcheng Wang <wangpengcheng.pp@bytedance.com> |
[RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (#103709)
These two extensions add addtional instructions for carryless multiplication with 32-bits elements and Vector-Scalar GCM instr
[RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (#103709)
These two extensions add addtional instructions for carryless multiplication with 32-bits elements and Vector-Scalar GCM instructions.
Please see https://github.com/riscv/riscv-isa-manual/pull/1306.
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Revision tags: llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init |
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#
70e7d26e |
| 23-Jul-2024 |
Alex Bradbury <asb@igalia.com> |
[RISCV] Mark zacas as experimental again due to unresolved ABI issue (#99898)
As discussed at the last sync-up call, mark Zacas as experimental until
this ABI issue is resolved
<https://github.com
[RISCV] Mark zacas as experimental again due to unresolved ABI issue (#99898)
As discussed at the last sync-up call, mark Zacas as experimental until
this ABI issue is resolved
<https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/444>.
Don't return Zacas in getHostCPUFeatures (leaving a TODO there) as even if requesting detection of "native" features, the user likely doesn't want to automatically opt in to experimental codegen.
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#
58c7df90 |
| 16-Jul-2024 |
Yeting Kuo <46629943+yetingk@users.noreply.github.com> |
[RISCV] Bump the version of Zicfilp/Zicfiss to 1.0 (#98891)
Both of them are ratified now.
https://wiki.riscv.org/display/HOME/Ratified+Extensions
This patch does not set them to non-experimenta
[RISCV] Bump the version of Zicfilp/Zicfiss to 1.0 (#98891)
Both of them are ratified now.
https://wiki.riscv.org/display/HOME/Ratified+Extensions
This patch does not set them to non-experimental, since Zicfilp lacks
lld support and Zicfiss also lacks compiler-rt/libunwind support.
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#
cd6750fa |
| 11-Jul-2024 |
Shao-Ce SUN <sunshaoce@outlook.com> |
[RISCV][NFC] Add a newline when using --print-enabled-extensions (#98425)
The `--print-enabled-extensions` has been introduced in the
https://github.com/llvm/llvm-project/pull/98207 , but it seems
[RISCV][NFC] Add a newline when using --print-enabled-extensions (#98425)
The `--print-enabled-extensions` has been introduced in the
https://github.com/llvm/llvm-project/pull/98207 , but it seems to be
missing a newline in the end.
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#
3c5f929a |
| 11-Jul-2024 |
R <rqou00@gmail.com> |
[RISCV] Add QingKe "XW" compressed opcode extension (#97925)
This extension consists of 8 additional 16-bit compressed forms for
existing standard load/store opcodes.
These opcodes are found in
[RISCV] Add QingKe "XW" compressed opcode extension (#97925)
This extension consists of 8 additional 16-bit compressed forms for
existing standard load/store opcodes.
These opcodes are found in some RISC-V microcontrollers from WCH /
Nanjing Qinheng Microelectronics.
As discussed in the Discourse forums, this uses incompatible extension
and opcode names vs the vendor binary toolchain. The chosen names
instead follow the conventions for other vendor extensions listed on the
"riscv-non-isa" project.
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#
eee5d2d3 |
| 10-Jul-2024 |
Michael Maitland <michaeltmaitland@gmail.com> |
[RISCV] Add ability to list extensions enabled for a target (#98207)
bb83a3d introduced `--print-enabled-extensions` command line option for
AArch64. This patch introduces RISC-V support for this o
[RISCV] Add ability to list extensions enabled for a target (#98207)
bb83a3d introduced `--print-enabled-extensions` command line option for
AArch64. This patch introduces RISC-V support for this option. This patch
adds documentation for this option.
`riscvExtensionsHelp` is renamed to `printSupportedExtensions` to by
synonymous with AArch64 and so it is clear what that function does.
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#
90d79e25 |
| 09-Jul-2024 |
Philip Reames <preames@rivosinc.com> |
Reapply "[RISCV] Remove experimental from Ztso. (#96465)"
This was reverted in f985a8826bfa4ca3d23e654185de35e30ea6dc79. Since that, the default WMO lowering has moved to A67 compatible, the ABI at
Reapply "[RISCV] Remove experimental from Ztso. (#96465)"
This was reverted in f985a8826bfa4ca3d23e654185de35e30ea6dc79. Since that, the default WMO lowering has moved to A67 compatible, the ABI attribute emission has landed (off by default), and the LLD change to merge said attributes have landed. Our ztso lowering is believed to also be A67 compatible, and no known issues remain.
Original commit message:
Ztso 1.0 was ratified in January 2023. Documentation: https://github.com/riscv/riscv-isa-manual/blob/main/src/ztso-st-ext.adoc
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#
32597685 |
| 09-Jul-2024 |
Jianjian Guan <jacquesguan@me.com> |
[RISCV] Remove experimental for bf16 extensions (#97996)
They are already ratified now.
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#
87de4975 |
| 02-Jul-2024 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Remove IgnoreUnknown from RISCVISAInfo::parseArchString. (#97372)
This isn't used in tree, and thus I don't know what the expectations for
its behavior really are. The original usage of thi
[RISCV] Remove IgnoreUnknown from RISCVISAInfo::parseArchString. (#97372)
This isn't used in tree, and thus I don't know what the expectations for
its behavior really are. The original usage of this feature has been replaced
by parseNormalizedArchString.
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#
dade11f5 |
| 27-Jun-2024 |
Michael Maitland <michaeltmaitland@gmail.com> |
[RISCV] Bump Pointer Masking extension version (#96715)
These extensions had their version number bumped and still experimental
(under public review). I didn't see anything in the [commit
history]
[RISCV] Bump Pointer Masking extension version (#96715)
These extensions had their version number bumped and still experimental
(under public review). I didn't see anything in the [commit
history](https://github.com/riscv/riscv-j-extension/commits/master/)
since #79929 that would warrant a change to the implementation of
pointer masking in the compiler.
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#
f985a882 |
| 24-Jun-2024 |
Philip Reames <preames@rivosinc.com> |
Revert "[RISCV] Remove experimental from Ztso. (#96465)"
This reverts commit 9cd6ef4b8a5c843ef491437c765d4cb2ff2f8fe3. See discussion on review thread.
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#
9cd6ef4b |
| 24-Jun-2024 |
Yingwei Zheng <dtcxzyw2333@gmail.com> |
[RISCV] Remove experimental from Ztso. (#96465)
Ztso 1.0 was ratified in January 2023.
Documentation:
https://github.com/riscv/riscv-isa-manual/blob/main/src/ztso-st-ext.adoc
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#
76254656 |
| 21-Jun-2024 |
Jianjian Guan <jacquesguan@me.com> |
[RISCV] Make M imply Zmmul (#95070)
According to the spec, M implies Zmmul.
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Revision tags: llvmorg-18.1.8 |
|
#
2fe72385 |
| 12-Jun-2024 |
Monad <yanwqmonad@gmail.com> |
[RISCV] Add Smcsrind and Sscsrind extension (#93952)
Specification link:
https://github.com/riscv/riscv-isa-manual/blob/main/src/indirect-csr.adoc
Some CSRs (`*ireg` and `*iselect`) in Smcsrin
[RISCV] Add Smcsrind and Sscsrind extension (#93952)
Specification link:
https://github.com/riscv/riscv-isa-manual/blob/main/src/indirect-csr.adoc
Some CSRs (`*ireg` and `*iselect`) in Smcsrind/Sscsrind extensions are
originally defined as part of the Smaia/Ssaia extensions and are already
supported in LLVM. The missing CSRs (`*ireg2` to `*ireg6` for `m`, `s`,
and `vs`) are added in this PR.
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#
307d91ee |
| 12-Jun-2024 |
Monad <yanwqmonad@gmail.com> |
[RISCV] Add smcdeleg and ssccfg extensions (#95163)
Specification:
https://github.com/riscv/riscv-isa-manual/blob/main/src/smcdeleg.adoc
`Ssccfg` introduces one new CSR `scountinhibit`.
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#
1bebb993 |
| 11-Jun-2024 |
Pengcheng Wang <wangpengcheng.pp@bytedance.com> |
[RISCV] Add B extension (#76893)
It seems that we have `B` extension again: https://github.com/riscv/riscv-b
According to the spec, `B` extension represents the collection of the `Zba`, `Zbb`, `Zbs
[RISCV] Add B extension (#76893)
It seems that we have `B` extension again: https://github.com/riscv/riscv-b
According to the spec, `B` extension represents the collection of the `Zba`, `Zbb`, `Zbs` extensions.
Though it hasn't been ratified, I set its version to `1.0`.
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Revision tags: llvmorg-18.1.7 |
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#
6b744496 |
| 03-Jun-2024 |
AlexGhiti <AlexGhiti@users.noreply.github.com> |
[RISCV] Remove experimental from Zabha (#93831)
The Zabha extension was ratified in April 2024.
Co-authored-by: Alexandre Ghiti <alexghiti@rivosinc.com>
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#
8be079cd |
| 21-May-2024 |
Brandon Wu <brandon.wu@sifive.com> |
[RISCV] Bump Zaamo and Zalrsc to version 1.0 (#91556)
The ratified information can be found here:
https://wiki.riscv.org/display/HOME/Ratified+Extensions
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