[RISCV] Add MIPS extensions (#121394)

Adding two extensions for MIPS p8700 CPU:
1. cmove (conditional move)
2. lsp (load/store pair)

The official product page here:
https://mips.com/produc

[RISCV] Add MIPS extensions (#121394)

Adding two extensions for MIPS p8700 CPU:
1. cmove (conditional move)
2. lsp (load/store pair)

The official product page here:
https://mips.com/products/hardware/p8700

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[RISCV] Renaming muladdi to muliadd as per v0.5 spec. (#124237)

muliadd is more relevant to the operation performed, i.e. multiply by
immediate.

The latest spec can be found at:
https://github.com/

[RISCV] Renaming muladdi to muliadd as per v0.5 spec. (#124237)

muliadd is more relevant to the operation performed, i.e. multiply by
immediate.

The latest spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

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[RISCV] Add Qualcomm uC Xqcilo (Large Offset Load Store) extension (#123881)

This extension adds eight 48 bit load store instructions.

The current spec can be found at:
https://github.com/quic/r

[RISCV] Add Qualcomm uC Xqcilo (Large Offset Load Store) extension (#123881)

This extension adds eight 48 bit load store instructions.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>

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[RISCV] Add Qualcomm uC Xqciint (Interrupts) extension (#122256)

This extension adds eleven instructions to accelerate interrupt
servicing.

The current spec can be found at:
https://github.com/

[RISCV] Add Qualcomm uC Xqciint (Interrupts) extension (#122256)

This extension adds eleven instructions to accelerate interrupt
servicing.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>

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[RISCV] Add Qualcomm uC Xqcicm (Conditional Move) extension (#121752)

The Qualcomm uC Xqcicm extension adds 13 conditional move instructions.

The current spec can be found at:
https://github.co

[RISCV] Add Qualcomm uC Xqcicm (Conditional Move) extension (#121752)

The Qualcomm uC Xqcicm extension adds 13 conditional move instructions.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>

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[RISCV] Add support of Sdext,Sdtrig extentions (#120936)

`Sdext` and `Sdtrig` are RISC-V extensions related to debugging.

The full specification can be found at

https://github.com/riscv/riscv-

[RISCV] Add support of Sdext,Sdtrig extentions (#120936)

`Sdext` and `Sdtrig` are RISC-V extensions related to debugging.

The full specification can be found at

https://github.com/riscv/riscv-debug-spec/releases/download/1.0.0-rc4/riscv-debug-specification.pdf

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[RISCV] Add Qualcomm uC Xqcicli (Conditional Load Immediate) extension (#121292)

This extension adds 12 instructions that conditionally load an immediate
value.

The current spec can be found at:

[RISCV] Add Qualcomm uC Xqcicli (Conditional Load Immediate) extension (#121292)

This extension adds 12 instructions that conditionally load an immediate
value.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

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[RISCV] Add Qualcomm uC Xqciac (Load-Store Adress calculation) extension (#121037)

This extension adds 3 instructions that perform load-store address
calculation.

The current spec can be found a

[RISCV] Add Qualcomm uC Xqciac (Load-Store Adress calculation) extension (#121037)

This extension adds 3 instructions that perform load-store address
calculation.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>

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[RISCV] Add ISAInfoTest tests for a few XQCI extensions (#120060)

Missed out adding rv32 only support test checks for a few of the
extensions.

[RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (#119823)

This extension adds 6 instructions that can do multi-word load/store.

The current spec can be found at:
https://github.c

[RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (#119823)

This extension adds 6 instructions that can do multi-word load/store.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

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[RISCV] Add Qualcomm uC Xqcics(Conditional Select) extension (#119504)

The Qualcomm uC Xqcics extension adds 8 conditional select instructions.

The current spec can be found at:
https://github.c

[RISCV] Add Qualcomm uC Xqcics(Conditional Select) extension (#119504)

The Qualcomm uC Xqcics extension adds 8 conditional select instructions.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>

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[RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (#118113)

This extension adds 11 instructions that perform integer arithmetic.

The current spec can be found at:
https://github.com/quic/risc

[RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (#118113)

This extension adds 11 instructions that perform integer arithmetic.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

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[RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store) extension (#117987)

This extension adds 8 load/store instructions with a scaled index
addressing mode.

The current spec can be found at:
http

[RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store) extension (#117987)

This extension adds 8 load/store instructions with a scaled index
addressing mode.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

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[RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169)

The Qualcomm uC Xqcicsr extension adds 2 instructions that can read and
write CSRs.

The current spec can be found at:
https://github.co

[RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169)

The Qualcomm uC Xqcicsr extension adds 2 instructions that can read and
write CSRs.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

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[RISCV] Support `svukte` extension (#115657)

This is the extension for "Address-Independent Latency of User-Mode
Faults to Supervisor Addresses".
Spec: https://github.com/riscv/riscv-isa-manual/pu

[RISCV] Support `svukte` extension (#115657)

This is the extension for "Address-Independent Latency of User-Mode
Faults to Supervisor Addresses".
Spec: https://github.com/riscv/riscv-isa-manual/pull/1564,
https://lf-riscv.atlassian.net/browse/RVS-2977
The spec states that the `svukte` depends on `sv39`, but we don't have
`sv39` yet, so I didn't add it to the implied list.

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[RISCV] Make A implies Zaamo and Zalrsc (#116907)

Ref:
https://github.com/riscv/riscv-isa-manual/blob/main/src/a-st-ext.adoc.

[RISCV] Fix typo in RISCVISAInfoTest.cpp. NFC.

ExtsRV32G -> ExtsRV64G.

[RISCV] Zabha/Zacas implies Zaamo (#115694)

The Zabha/Zacas extension depends upon the Zaamo extension.
Ref: https://github.com/riscv/riscv-isa-manual/blob/main/src/zacas.adoc
https://github.com/

[RISCV] Zabha/Zacas implies Zaamo (#115694)

The Zabha/Zacas extension depends upon the Zaamo extension.
Ref: https://github.com/riscv/riscv-isa-manual/blob/main/src/zacas.adoc
https://github.com/riscv/riscv-isa-manual/blob/main/src/zabha.adoc.

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[RISCV] Add Smdbltrp and Ssdbltrp extension (#111837)

Smdbltrp and Ssdbltrp supports are added in this PR.
Specification link(Smdbltrp) :
[https://github.com/riscv/riscv-isa-manual/blob/main/src/s

[RISCV] Add Smdbltrp and Ssdbltrp extension (#111837)

Smdbltrp and Ssdbltrp supports are added in this PR.
Specification link(Smdbltrp) :
[https://github.com/riscv/riscv-isa-manual/blob/main/src/smdbltrp.adoc](url)
Specification link(Ssdbltrp) :
[https://github.com/riscv/riscv-isa-manual/blob/main/src/ssdbltrp.adoc](url)

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[RISCV] Allow crypto features to imply dependents (#112659)

This relationship is a logical dependency.

Note Zvbc and Zvknhb. They are explicitly called out in the spec as
requiring 64 bits:
-

[RISCV] Allow crypto features to imply dependents (#112659)

This relationship is a logical dependency.

Note Zvbc and Zvknhb. They are explicitly called out in the spec as
requiring 64 bits:
-
https://github.com/riscv/riscv-crypto/blob/56ed7952d13eb5bdff92e2b522404668952f416d/doc/vector/riscv-crypto-spec-vector.adoc

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[RISCV] Mark RVB23U64 and RVB23S64 as non-experimental (#113918)

The specification was recently ratified

<https://github.com/riscv/riscv-profiles/blob/main/src/rvb23-profile.adoc>.

[RISCV] Mark the RVA23S64 and RVA23U64 profiles as non-experimental (#113826)

All of the extensions used by these profile are themselves
non-experimental, and RVA23 was just ratified

<https://ri

[RISCV] Mark the RVA23S64 and RVA23U64 profiles as non-experimental (#113826)

All of the extensions used by these profile are themselves
non-experimental, and RVA23 was just ratified

<https://riscv.org/announcements/2024/10/risc-v-announces-ratification-of-the-rva23-profile-standard/>.

<https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc>

We lack a way of expressing `Ss1p13` (supervisor architecture 1.13), but
this is a problem we have for RVA22 (Ss1p12) and RVA20 (Ss1p11) so I
don't feel it's a blocker.

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[RISCV]Add svvptc extension (#113882)

[RISCV] Add the Sha extension (#113820)

This was introduced in the now-ratified RVA23 profile (and also added to
the RVA22 text) as a simple way of referring to H plus the set of
supervisor extens

[RISCV] Add the Sha extension (#113820)

This was introduced in the now-ratified RVA23 profile (and also added to
the RVA22 text) as a simple way of referring to H plus the set of
supervisor extensions required by RVA23.
https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc

This patch simply defines the extension. The next patch will adjust the
RVA23 profile to use it, and at that point I think we will be ready to
mark RVA23 as non-experimental.

Note that I haven't made it so if you enable all extensions that
constitute Sha, Sha is implied. Per #76893 (adding 'B'), the concern is
making this implication might break older external assemblers. Perhaps
this is less of a concern given the relative frequency of
`-march=${foo}_zba_zbb_zbs` vs the collection of H extensions. If we did
want to add that implication, we'd probably want to add it in a separate
patch so it can be easily reverted if found to cause problems.

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[RISCV] Mark pointer masking extensions as non-experimental (#113618)

These extensions were ratified very recently.

<https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154732/Ratified+Extens

[RISCV] Mark pointer masking extensions as non-experimental (#113618)

These extensions were ratified very recently.

<https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154732/Ratified+Extensions>

I've ensured we have definitions for all extensions in the document
<https://drive.google.com/file/d/159QffOTbi3EEbdkKndYRZ2c46D25ZLmO/view?usp=drive_link>.
There are no additional CSRs.

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