Overhaul the TargetMachine and LLVMTargetMachine Classes (#111234)

Following discussions in #110443, and the following earlier discussions
in https://lists.llvm.org/pipermail/llvm-dev/2017-October/

Overhaul the TargetMachine and LLVMTargetMachine Classes (#111234)

Following discussions in #110443, and the following earlier discussions
in https://lists.llvm.org/pipermail/llvm-dev/2017-October/117907.html,
https://reviews.llvm.org/D38482, https://reviews.llvm.org/D38489, this
PR attempts to overhaul the `TargetMachine` and `LLVMTargetMachine`
interface classes. More specifically:
1. Makes `TargetMachine` the only class implemented under
`TargetMachine.h` in the `Target` library.
2. `TargetMachine` contains target-specific interface functions that
relate to IR/CodeGen/MC constructs, whereas before (at least on paper)
it was supposed to have only IR/MC constructs. Any Target that doesn't
want to use the independent code generator simply does not implement
them, and returns either `false` or `nullptr`.
3. Renames `LLVMTargetMachine` to `CodeGenCommonTMImpl`. This renaming
aims to make the purpose of `LLVMTargetMachine` clearer. Its interface
was moved under the CodeGen library, to further emphasis its usage in
Targets that use CodeGen directly.
4. Makes `TargetMachine` the only interface used across LLVM and its
projects. With these changes, `CodeGenCommonTMImpl` is simply a set of
shared function implementations of `TargetMachine`, and CodeGen users
don't need to static cast to `LLVMTargetMachine` every time they need a
CodeGen-specific feature of the `TargetMachine`.
5. More importantly, does not change any requirements regarding library
linking.

cc @arsenm @aeubanks

show more ...

[AArch64] Initial sched model for Neoverse N3 (#106371)

References:

* Arm Neoverse N3 Software Optimization Guide
* Arm A64 Instruction Set for A-profile architecture

[AArch64] Ensure Neoverse-N2 scheduling model includes all SVE pseudos.

Similar to #84187, this enables the existing test we have for checking the
scheduling info of the pseudos matches the real ins

[AArch64] Ensure Neoverse-N2 scheduling model includes all SVE pseudos.

Similar to #84187, this enables the existing test we have for checking the
scheduling info of the pseudos matches the real instructions, and adjusts the
scheduling info in the NeoverseN2 model to make sure all cases were handled.

show more ...

[AArch64] Ensure Neoverse V1 scheduling model includes all SVE pseudos. (#84187)

With the many pseudos used in SVE codegen it can be too easy to miss
instructions. This enables the existing test we

[AArch64] Ensure Neoverse V1 scheduling model includes all SVE pseudos. (#84187)

With the many pseudos used in SVE codegen it can be too easy to miss
instructions. This enables the existing test we have for checking the
scheduling info of the pseudos matches the real instructions, and
adjusts the scheduling info in the NeoverseV1 model to make sure all are
handled. In the cases I could I opted to use the same info as in the
NeoverseV2 model, to keep the differences smaller.

show more ...

[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#66295)

This will make it easy for callers to see issues with and fix up calls
to createTargetMachine after a future chang

[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#66295)

This will make it easy for callers to see issues with and fix up calls
to createTargetMachine after a future change to the params of
TargetMachine.

This matches other nearby enums.

For downstream users, this should be a fairly straightforward
replacement,
e.g. s/CodeGenOpt::Aggressive/CodeGenOptLevel::Aggressive
or s/CGFT_/CodeGenFileType::

show more ...

[AArch64] Fix build on Windows after 57329ca9463

57329ca9463 added a .inc include within an unnamed namespace,
creating ::(unnamed namespace)::llvm in addition to ::llvm.
This confuses things on Win

[AArch64] Fix build on Windows after 57329ca9463

57329ca9463 added a .inc include within an unnamed namespace,
creating ::(unnamed namespace)::llvm in addition to ::llvm.
This confuses things on Windows.

show more ...

[AArch64] Ignore instructions not supported by CPU in AArch64SVESchedPseudoTest

When adding new Pseudos for instructions that are not supported
by the CPU for which the scheduler model is being test

[AArch64] Ignore instructions not supported by CPU in AArch64SVESchedPseudoTest

When adding new Pseudos for instructions that are not supported
by the CPU for which the scheduler model is being tested, the test fails
if these pseudos are not covered by the regex's in the scheduling model.

Rather than failing, this test should check that the CPU supports the
original instruction modelled by the pseudo. If not, the pseudo is
not relevant to the scheduling model being tested.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D156094

show more ...

[AArch64] Update SVE scheduling of some CPUs

* Update cortex-a510 and neoverse-v2 SVE scheduling so that pseudos
have the same instruction latency as original instruction.

Differential Revision

[AArch64] Update SVE scheduling of some CPUs

* Update cortex-a510 and neoverse-v2 SVE scheduling so that pseudos
have the same instruction latency as original instruction.

Differential Revision: https://reviews.llvm.org/D154084

show more ...